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AD9625 Datasheet(PDF) 49 Page - Analog Devices |
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AD9625 Datasheet(HTML) 49 Page - Analog Devices |
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49 / 56 page ![]() Data Sheet AD9625 Table 83. JESD204B Lane Control Register 3, Address 0x084 (Default = 0x54) Bit No. Access Bit Description 7 Unused. [6:4] RW Physical Lane F assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5 (default). 110: Logical Lane 6. 111: Logical Lane 7. 3 Unused. [2:0] RW Physical Lane E assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4 (default). 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7. Table 84. JESD204B Lane Control Register 4, Address 0x085 (Default = 0x76) Bit No. Access Bit Description 7 Unused. [6:4] RW Physical Lane H assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6. 111: Logical Lane 7 (default). 3 Unused. [2:0] RW Physical Lane G assignment. 000: Logical Lane 0. 001: Logical Lane 1. 010: Logical Lane 2. 011: Logical Lane 3. 100: Logical Lane 4. 101: Logical Lane 5. 110: Logical Lane 6 (default). 111: Logical Lane 7. Table 85. Unused, Address 0x088 (Default = 0x00) Bit No. Access Bit Description [7:0] RW Unused. Table 86. Unused, Address 0x089 (Default = 0x00) Bit No. Access Bit Description [7:0] RW Unused. Rev. 0 | Page 49 of 56 |
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