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Data Sheet

AD9625

DIGITAL DOWNCONVERTERS (DDC)

Figure 31. Digital Downconverters

The AD9625 architecture includes two DDCs, each designed to

extract a portion of the full digital spectrum captured by the

ADC. Each tuner consists of an independent frequency

synthesizer and quadrature mixer; a chain of low-pass filters for

rate conversion follows these components. Assuming a

sampling frequency of 2.000 GHz, the frequency synthesizer

(10-bit NCO) allows for 1024 discrete tuning frequencies,

ranging from −0.999 GHz to +1.000 GHz, in steps of 2000/1024

= 1.953 MHz. The low-pass filters allow for two modes of

decimation.

•

A high bandwidth mode, 192 MHz wide (from −96 MHz

to +96 MHz), sampled at 2.0 GHz/8 = 250 MHz for the I

and Q branches separately. The 16-bit samples from the I

and Q branches are transmitted through a dedicated

JESD204B interface.

•

A low bandwidth mode, 96 MHz wide (from −48 MHz to

+48 MHz), sampled at 2.0 GHz/16 = 125 MHz for the I and

Q branches separately. The 16-bit samples from the I and Q

branches are transmitted through a dedicated JESD204B

interface.

By design, all of the blocks operate at a single clock frequency of

2.0 GHz/8 = 250 MHz.

Each filter stage includes a gain control block that is programmable

by the user. The gain varies from 0 dB to 18 dB, in steps of 6 dB,

and the gain is applied before final scaling and rounding. The

gain control feature may be useful in cases where the tuner

filters out a strong out-of-band interferer, leaving a weak in-

band signal.

FREQUENCY SYNTHESIZER AND MIXER

For a sampling rate of 2.000 GHz, the synthesizer (10-bit NCO)

outputs one of 1024 possible complex frequencies from

−0.999 GHz to +1.000 GHz. The synthesizer employs the direct

digital synthesis technique, using look-up sine tables and a

phase accumulator. The user specifies the tuner frequency by

writing to a 10-bit phase increment register.

HIGH BANDWIDTH DECIMATOR

The first filter stage is designed for a rate reduction factor of 8,

yielding a sample rate of 2.000 GHz/8 = 250 MHz. To achieve a

combination of low complexity and low clock rate, the DDC

employs a decimate-by-8 polyphase fuse filter that receives

eight 13-bit samples from the mixer block at every clock cycle.

The block design provides user specified gain control, from 0 dB to

18 dB in steps of 6 dB. The gain is applied before final scaling

and rounding to 16 bits.

Figure 32. Magnitude Response of the Decimate-by-8 Polyphase Fuse Filter

Filter performance is shown in Figure 32 and Figure 34. The

filter yields an effective bandwidth of 96 MHz, with a transition

band of 125 − 96 = 29 MHz. Hence, the two-sided complex

bandwidth of the filter is 192 MHz.

A rejection ratio of 85 dB ensures that the seven aliases that fold

back into the pass band yield an SNR of 85 dB − 10log10(7) =

76.5 dB, which ensures that the aliases remain sufficiently below

the noise floor of the input signal. The pass-band ripple is

±0.05 dB, as shown in Figure 33.

SYNTHESIZER

NCO

12-BIT ADC

@ 2.0GSPS

DECIMATION

BY 8

GAIN SELECT:

0dB, 6dB, 12dB, 18dB

MODE SELECT:

96MHz OR 192MHz BW

MIXER

8 × 12-BIT

@ 250MHz

DECIMATION

BY 8

DECIMATION

BY 2

8 × 13-BIT

@ 250MHz

8 × 12-BIT

@ 250MHz

8 × 13-BIT

@ 250MHz

16-BIT @ 250MHz

16-BIT

@ 125MHz

16-BIT

@ 125MHz

I-PHASE

16-BIT @ 250MHz

Q-PHASE

TUNER SELECT:

–1.0GHz TO +1.0GHz

GAIN SELECT:

0dB, 6dB,

12dB, 18dB

FRAMER

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

fS/2

FREQUENCY (MHz)

Rev. 0 | Page 21 of 56

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