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Data Sheet

AD9625

Figure 47. fS × 2 Application Layer (Receive)

FRAME ALIGNMENT CHARACTER INSERTION

Frame alignment character insertion (FACI) is defined in the

FACI only when it is used as a test feature.

The FACI disable bit is located in Register 0x05F, Bit 1. Use the

following settings:

•

Setting Bit 1 to 0 = FACI enabled

•

Setting Bit 1 to 1 = FACI disabled

THERMAL CONSIDERATIONS

Because of the high power nature of the device, it is critical to

provide airflow and/or install a heat sink when operating at a

high temperature. This ensures that the maximum case

temperature does not exceed 85°C.

POWER SUPPLY CONSIDERATIONS

The AD9625 must be powered by the following two supplies:

AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 =

DRVDD2 = 2.5 V. An optional DVDDIO and SPI_DVDDIO

may be required at 2.5 V.

For applications requiring an optimal high power efficiency and

low noise performance, it is recommended that ADP2386

switching regulator is used to convert the 12 V input rail into

two intermediate rails (2.1 V and 3.6 V). These intermediate

rails are then postregulated by very low noise, low dropout (LDO)

regulators (ADP1740, ADP7104, and ADP125). Figure 48

shows the recommended method.

APPLICATION

LAYER

DATA LINK,

TRANSPORT,

AND PHY LAYERS

fS × 2 APPLICATION LAYER (RECEIVE)

4/5 RATE EXCHANGE

CUSTOMER APPLICATION

USER

DEFINED

ADC SAMPLE N

(12 BITS)

ADC SAMPLE N + 1

(12 BITS)

ADC SAMPLE N + 2

(12 BITS)

ADC SAMPLE N + 3

(12 BITS)

48 BITS

fS/4

64 BITS

fS/5

64 BITS

fS/5

ADC SAMPLE N

(12 BITS)

ADC SAMPLE N + 1

(12 BITS)

ADC SAMPLE N + 2

(12 BITS)

ADC SAMPLE N + 3

(12 BITS)

ADC SAMPLE N + 4

(12 BITS)

(4 BITS)

S[N][11:0], S[N + 1][11:8]

(16 BITS)

S[N + 1][7:0], S[N + 2][11:4]

(16 BITS)

S[N + 2][3:0], S[N + 3][11:0]

(16 BITS)

S[N + 4][11:0], UD[3:0]

(16 BITS)

JESD SAMPLE N

(16 BITS)

JESD SAMPLE N + 1

(16 BITS)

JESD SAMPLE N + 2

(16 BITS)

JESD SAMPLE N + 3

(16 BITS)

JESD204B FRAMER + PHY

(M = 1; L = 8; S = 4; F = 1; N = 16; N' = 16; CF = 0; SCR = 0, 1; HD = 1; K = SEE SPEC

Rev. 0 | Page 33 of 56

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