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80960JD Datasheet(PDF) 76 Page - Intel Corporation |
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80960JD Datasheet(HTML) 76 Page - Intel Corporation |
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76 / 86 page ![]() CLKIN ALE#, ADS#, ALE#,W/R#, RESET# LOCK#/ STEST VCC DT/R# FAIL# First Bus Activity Valid (Output) ONCE# AD31:0, A3:2,D/C# (Note 1) Idle (Note 2) HOLD Valid Input (Note 3) BE3:0#, DEN#, BLAST# Valid Output (Note 3) HOLDA V 10,000 CLKIN periods, for PLL stabilization. CC and CLKIN stable to RESET High, minimum Built-in self-test (Note 4) (Input) 1. The processor asserts FAIL# during built-in self-test. When self- test passes, the FAIL# pin is deasserted.The processor also asserts FAIL# during the bus confidence test. When the bus confidence test passes, FAIL# is deasserted and the processor begins user program execution. Notes: 2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure. 3. Since the bus is idle, hold requests are honored during reset and built-in self-test. WIDTH/HLTD1:0 4. When selected, built-in self test requires approximately (in CLKIN periods): 393,000 for 80960JT, 580,012 for the 80960JC, 1,176,025 for the 80960JS, 207,000 for 80960JD, and 414,000 for 80960JA/JF. |
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