80960JD datasheet(22/86 Pages) INTEL

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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor

Datasheet

TDO

R(Q)

HQ)

P(Q)

TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling

edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At

other times, TDO floats. TDO does not float during ONCE mode.

TRST#

A(L)

TEST RESET asynchronously resets the Test Access Port (TAP) controller function

of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan

feature, connect a pull-down resistor between this pin and VSS. When TAP is not

used, this pin must be connected to VSS; however, no resistor is required. See

Section 4.3, “Connection Recommendations” on page 36.

TMS

S(L)

TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of

the test logic for IEEE 1149.1 Boundary Scan testing.

VCC

–

POWER pins intended for external connection to a VCC board plane.

VCCPLL

–

PLL POWER is a separate VCC supply pin for the phase lock loop clock generator. It

is intended for external connection to the VCC board plane. In noisy environments,

add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on

timing relationships.

VCC5

–

5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O

buffers. This signal should be connected to +5 V for use with inputs which exceed

3.3 V. When all inputs are from 3.3 V components, this pin should be connected to

3.3 V.

VSS

–

GROUND pins intended for external connection to a VSS board plane.

–

NO CONNECT pins. Do not make any system connections to these pins.

Table 10. Pin Description—Interrupt Unit Signals

NAME

TYPE

DESCRIPTION

XINT[7:0]#

A(E/L)

EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT[7:0]#

pins may be configured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs

may be programmed to be level (low) or edge (falling) sensitive.

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins

are level sensitive in this mode.

Mixed Mode: The XINT[7:5]# pins act as dedicated sources and the XINT[4:0]# pins

act as the five most significant bits of a vectored source. The least significant bits of

the vectored source are set to 0102 internally.

Unused external interrupt pins should be connected to VCC.

NMI#

A(E)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

NMI# is the highest priority interrupt source and is falling edge-triggered. when NMI#

is unused, it should be connected to VCC.

Table 9.

Pin Description—Processor Control Signals, Test Signals, and Power (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

80960JD Datasheet(PDF) 22 Page - Intel Corporation

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