80960JD datasheet(36/86 Pages) INTEL

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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor

Datasheet

4.3

Connection Recommendations

For clean on-chip power distribution, VCC and VSS pins separately feed the device’s functional

units. Power and ground connections must be made to all 80960Jx power and ground pins. On the

circuit board, every VCC pin should connect to a power plane and every VSS pin should connect to

a ground plane. Place liberal decoupling capacitance near the 80960Jx, since the processor may

cause transient power surges.

The 80960JS/JC/JT processors are produced on Intel’s advanced CMOS process. Proper bulk

decoupling must be used to prevent device damage during initial power up and during transitions

from low power mode to normal processor operation. Power supply behavior during these

transitions may cause the power supply to exceed the maximum VCC specification and may cause

device damage.

Pay special attention to the Test Reset (TRST#) pin. It is essential that the JTAG Boundary Scan

Test Access Port (TAP) controller initializes to a known state whether it may be used or not. When

the JTAG Boundary Scan function may be used, connect a pull-down resistor between the TRST#

pin and VSS. When the JTAG Boundary Scan function may not be used (even for board-level

testing), connect the TRST# pin to VSS.

Do not connect the TDI, TDO, and TCK pins when the TAP Controller may not be used.

Note:

Pins identified as NC must not be connected in the system.

4.4

VCC5 Pin Requirements (VDIFF)

In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5

pin directly to the 3.3 V VCC plane.

In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V

components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation, and

prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and its

3.3 V VCC pins must not exceed 2.25 V. When this requirement is not met, current flow through the

pin may exceed the value at which the processor is damaged. Instances when the voltage may

exceed 2.25 V is during power up or power down, where one source reaches its level faster than the

other, briefly causing an excess voltage differential. Another instance is during steady-state

operation, where the differential voltage of the regulator (provided a regulator is used) cannot be

maintained within 2.25 V. Two methods are possible to prevent this from happening:

• Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V.

or:

• As shown in Figure 8, place a 100

Ω resistor in series with the VCC5 pin to limit the current

through VCC5.

Figure 8. VCC5 Current-Limiting Resistor

+5 V (±0.25 V)

VCC5 Pin

100

Ω

(±5%, 0.5 W)

80960JD Datasheet(PDF) 36 Page - Intel Corporation

80960JD Datasheet(HTML) 36 Page - Intel Corporation

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