80960JD datasheet(18/86 Pages) INTEL

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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor

Datasheet

Table 8.

Pin Description—External Bus Signals (Sheet 1 of 4)

NAME

TYPE

DESCRIPTION

AD[31:0]

I/O

S(L)

R(X)

H(Z)

P(Q)

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data

to and from memory. During an address (Ta) cycle, bits 31:2 contain a physical word

address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write

data is present on one or more contiguous bytes, comprising AD[31:24], AD[23:16],

AD[15:8] and AD[7:0]. During write operations, unused pins are driven to

determinate values.

SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the

number of data transfers during the bus transaction.

AD1

AD0

Bus Transfers

1 Transfer

2 Transfers

3 Transfers

4 Transfers

When the processor enters Halt mode, if the previous bus operation was a:

•

write — AD[31:2] are driven with the last data value on the AD bus.

•

read — AD[31:4] are driven with the last address value on the AD bus; AD[3:2]

are driven with the value of A[3:2] from the last data cycle.

Typically, AD[1:0] reflect the SIZE information of the last bus transaction (either

instruction fetch or load/store) that was executed before entering Halt mode.

ALE

R(0)

H(Z)

P(0)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

asserted during a Ta cycle and deasserted before the beginning of the Td state. It is

active HIGH and floats to a high impedance state during a hold cycle (Th).

ALE#

R(1)

H(Z)

P(1)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE# is

the inverted version of ALE. This signal gives the 80960Jx a high degree of

compatibility with existing 80960Kx systems.

ADS#

R(1)

H(Z)

P(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

The processor asserts ADS# for the entire Ta cycle. External bus control logic

typically samples ADS# at the end of the cycle.

A[3:2]

R(X)

H(Z)

P(Q)

ADDRESS[3:2] comprise a partial demultiplexed address bus.

32-bit memory accesses: the processor asserts address bits A[3:2] during Ta. The

partial word address increments with each assertion of RDYRCV# during a burst.

16-bit memory accesses: the processor asserts address bits A[3:1] during Ta with A1

driven on the BE1# pin. The partial short word address increments with each

assertion of RDYRCV# during a burst.

8-bit memory accesses: the processor asserts address bits A[3:0] during Ta, with

A[1:0] driven on BE[1:0]#. The partial byte address increments with each assertion of

RDYRCV# during a burst.

80960JD Datasheet(PDF) 18 Page - Intel Corporation

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