80960JD datasheet(80/86 Pages) INTEL

80 / 86 page

80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor

Datasheet

7.2

Boundary-Scan Register

The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and

HIGHZ pins.

Table 42 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that

contain ‘CTL’ select the direction of bidirectional pins or HIGHZ output pins. When a 1 is loaded

into the control cell, the associated pin(s) are HIGHZ or selected as input.

Figure 52. Bus States with Arbitration

Ti — IDLE STATE

Ta — ADDRESS STATE

Tw / Td — WAIT/DATA STATE

Tr — RECOVERY STATE

Th — HOLD STATE

To — ONCE STATE

READY — RDYRCV# ASSERTED

NOT READY — RDYRCV# NOT ASSERTED

BURST — BLAST# NOT ASSERTED

NO BURST — BLAST# ASSERTED

RECOVERED — RDYRCV# NOT ASSERTED

NOT RECOVERED — RDYRCV# ASSERTED

REQUEST PENDING — NEW TRANSACTION

NO REQUEST

— NO NEW TRANSACTION

HOLD — HOLD REQUEST ASSERTED

NO HOLD — HOLD REQUEST NOT ASSERTED

LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS

NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS

RESET — RESET# ASSERTED

ONCE — ONCE# ASSERTED

Tw/Td

HOLD AND

NOT LOCKED

HOLD

RECOVERED AND

NO REQUEST AND

(NO HOLD OR

LOCKED)

RECOVERED AND

REQUEST

PENDING AND (NO

HOLD OR LOCKED)

NO REQUEST

AND NO HOLD

RESET

NOT

RECOVERED

RECOVERED AND

HOLD AND NOT

LOCKED

READY AND NO BURST

(READY AND BURST)

OR NOT READY

REQUEST PENDING

AND (NO HOLD OR

LOCKED)

NO REQUEST

AND (NO HOLD

OR LOCKED)

ONCE & RESET

DEASSERTION

REQUEST

PENDING AND

NO HOLD

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