XTR111 datasheet(13/33 Pages) TI1

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XTR111

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SBOS375C

– NOVEMBER 2006 – REVISED JUNE 2011

EXPLANATION OF PIN FUNCTIONS

EF : The active low error flag (logic output) is

intended for use with an external pull-up to logic-high

VIN: This input is a conventional, noninverting,

for reliable operation when this output is used.

high-impedance input of the internal operational

However, it has a weak internal pull-up to 5V and can

amplifier (OPA). The internal circuitry is protected by

be left unconnected if not used.

clamp diodes to supplies. An additional clamp

connected to approximately 18V protects internal

OD: This control input has a 4

μA internal pull-up

circuitry. Place a small resistor in series with the input

disabling the output. A pull-down or short to GND is

to limit the current into the protection if voltage can be

required to activate the output. Controlling OD

present without the XTR111 being powered. Consider

reduces

output

glitches

during

power-on

and

a resistor value equal to RSET for bias current

power-off. This logic input controls the output. If not

cancellation.

used, connect to GND.

SET: The total resistance connected between this pin

The regulator is not affected by OD.

and

VIN

reference

sets

the

transconductance.

Additional series resistance can degrade accuracy

EXTERNAL CURRENT LIMIT

and drift. The voltage on this pin must not exceed

The XTR111 does not provide internal current limit for

14V because this pin is not protected to voltages

the case of when the external FET is forced to low

above this level.

impedance. The internal current source controls the

IS: This output pin is connected to the transistor

current, but a high current from IS to GND forces an

source of the external FET. The accuracy of the

internal voltage clamp between VSP and IS to turn

output current to IS is achieved by dynamic error

on. This results in a low resistance path and the

correction in the current mirror. This pin should never

current is only limited by the load impedance and the

be pulled more than 6.5V below the positive supply.

current capability of the external FET. A high current

An internal clamp is provided to protect the circuit;

can destroy the IC. With the current loop interrupted

however, it must be externally current-limited to less

(the load disconnected) the external MOSFET is fully

than 50mA.

turned on with large gate to source voltage stored in

the gate capacitance. In the moment the loop is

VG: The gate drive for the external FET is protected

closed (the load connected) current flows into the

against shorts to the supply and GND. The circuit is

load. But for the first few micro-seconds the MOSFET

clamped so that it will not drive more than 18V below

is still turned on and destructive current can flow,

the positive supply. The external FET should be

depending on the load impedance.

protected if its gate could be externally pulled beyond

its ratings.

An external current limit is recommended to protect

the XTR111 from this condition. Figure 37a shows an

REGF: The output of the regulator buffer can source

example of a current limit circuit. The current should

up to 5mA current, but has very limited (less than

be limited to 50mA. The 15

Ω resistor (R6) limits the

μA) sinking capability. The maximum short-circuit

current to approximately 37mA (33mA when hot). The

current is in the range of 15mA to 25mA, changing

PNP transistor should allow a peak current of several

over temperature.

hundred mA. An example device is the (KST)2907.

REGS: This pin is the sense input of the voltage

Power dissipation is not normally critical because the

regulator. It is referenced to an internal 3V reference

peak current duration is only a few micro-seconds.

circuit. The input bias current can be up to 2

μA. Avoid

However, observe the leakage current through the

capacitive loading of REGS that may compromise the

transistor from IS to VG. The addition of this current

loop stability of the voltage regulator.

limiting

transistor

and

R6 still require time to

discharge the gate of the external MOSFET. R7 and

VSP: The supply voltage of up to a maximum of 44V

C3 are added for this reason, as well as to limit the

allows operation in harsh industrial environment and

steepness of external distortion pulses. Additional

provides

headroom

for

easy

protection

against

EMI and over-voltage protection may be required

over-voltage. Use a large enough bypass capacitor (

according to the application.

100nF) and eventually a damping inductor or a small

resistor (5

Ω) to decouple the XTR111 supply from the

Figure 37b is a universal and basic current limiter

noise typically found on the 24V supplies.

circuit, using PNP or NPN transistors that can be

connected in the source (IS to S) or in the drain

output (in series with the current path). This circuit

does not contribute to leakage currents. Consider

adding an output filter like R7 and C3 in this limiter

circuit.

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