DDC114IRTCRG3 datasheet(21/37 Pages) TI1

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DDC114

SBAS255C − JUNE 2004 − REVISED APRIL 2009

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DATA FORMAT (FORMAT)

The serial output data is provided in an offset binary code

as shown in Table 9. The digital input pin FORMAT selects

how many bits are used in the output word. When

FORMAT is high (1), 20 bits are used. When FORMAT is

low (0), the lower 4 bits are truncated so that only 16 bits

are used. Note that the LSB size is 16 times bigger when

FORMAT = 0. An offset is included in the output to allow

slightly negative inputs, from board leakages for example,

from clipping the reading. This offset is approximately

0.4% of the positive full−scale.

Table 9. Ideal Output Code(1) vs Input Signal

INPUT

SIGNAL

IDEAL OUTPUT CODE

FORMAT = HIGH

(1)

IDEAL OUTPUT CODE

FORMAT = LOW

(0)

≥ 100% FS

1111 1111 1111 1111 1111

1111 1111 1111 1111

0.001531% FS

0000 0001 0000 0001 0000

0000 0001 0000 0001

0.001436% FS

0000 0001 0000 0000 1111

0000 0001 0000 0000

0.000191% FS

0000 0001 0000 0000 0010

0000 0001 0000 0000

0.000096% FS

0000 0001 0000 0000 0001

0000 0001 0000 0000

0% FS

0000 0001 0000 0000 0000

0000 0001 0000 0000

−0.3955% FS

0000 0000 0000 0000 0000

0000 0000 0000 0000

(1) Excludes the effects of noise, INL, offset, and gain errors.

DATA RETRIEVAL

In both the continuous and non-continuous modes of

operation, the data from the last conversion is available for

retrieval on the falling edge of DVALID (see Figure 20 and

Table 10, on page 22). Data is shifted out on the falling

edge of the data clock, DCLK. Make sure not to retrieve

data while CONV changes as this can introduce noise.

Stop activity on DCLK at least 10

µs before or after a CONV

transition.

Setting the FORMAT pin = 0 (16-bit output word) reduces

the time needed to retrieve data by 20%, since there are

fewer bits to shift out. This time reduction can be useful in

multichannel systems requiring only 16 bits of resolution.

CLK

DVALID

DCLK

DOUT

Input 4

MSB

Input 1

LSB

Input 4

LSB

Input 3

MSB

Input 3

LSB

Input 2

MSB

Input 2

LSB

Input 1

MSB

Input 4

MSB

Figure 20. Digital Interface Timing Diagram for Data Retrieval From a Single DDC114

Table 10. Timing for the DDC114 Data Retrieval

SYMBOL

DESCRIPTION

CLK = 4MHz, CLK_4X = 0

CLK = 4.8MHz, CLK_4X = 0

UNITS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

t18

Propagation Delay from Falling Edge of CLK to DVALID LOW

t19

Propagation Delay from Falling Edge of DCLK to DVALID HIGH

t20

Hold Time that DOUT is Valid Before the Falling Edge of DVALID

1.75

1.458

µs

t21

Hold Time that DOUT is Valid After Falling Edge of DCLK

t21A(1)

Propagation Delay from Falling Edge of DCLK to Valid DOUT

(1) With a maximum load of one DDC114 (4pF typical) with an additional load of 5pF.

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