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DDC114IRTCRG3 Datasheet(PDF) 3 Page - Texas Instruments

Part # DDC114IRTCRG3
Description  Quad Current Input, 20-Bit Analog-To-Digital Converter
PDF  37 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DDC114IRTCRG3 Datasheet(HTML) 3 Page - Texas Instruments

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DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
www.ti.com
3
ELECTRICAL CHARACTERISTICS
At TA = +25
°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted.
Low-Power Mode: TINT = 400
µs and CLK = 4MHz; High-Speed Mode: TINT = 320µs and CLK = 4.8MHz.
Low-Power Mode
High-Speed Mode
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT RANGE
Range 0
10.2
12
13.8
∗(1)
∗
∗
pC
Range 1
47.5
50
52.5
∗
∗
∗
pC
Range 2
95
100
105
∗
∗
∗
pC
Range 3
142.5
150
157.5
∗
∗
∗
pC
Range 4
190
200
210
∗
∗
∗
pC
Range 5
237.5
250
262.5
∗
∗
∗
pC
Range 6
285
300
315
∗
∗
∗
pC
Range 7
332.5
350
367.5
∗
∗
∗
pC
Negative Full-Scale Range
−0.4% of Positive Full-Scale Range
∗
pC
Input Current(2)
750
∗
µA
DYNAMIC CHARACTERISTICS
Data Rate
2.5
3.125
kSPS
Integration Time, TINT
Continuous Mode
400
1,000,000
320
∗
µS
Integration Time, TINT
Non-continuous Mode, Range 1 to 7
50
∗
µS
System Clock Input (CLK)
CLK_4X = 0
4
4.8
MHz
CLK_4X = 1
16
19.2
MHz
Data Clock (DCLK)
16
∗
MHz
ACCURACY
Noise, Low-Level Input(3)
CSENSOR(4) = 50pF, Range 5 (250pC)
5.2
6.5
5.5
7
ppm of
FSR(5), rms
Integral Linearity Error(6)
±0.01% Reading ± 0.5ppm FSR, typ
∗
Integral Linearity Error(6)
±0.025% Reading ± 1.0ppm FSR, max
∗
Resolution
FORMAT = 1
20
∗
Bits
Resolution
FORMAT = 0
16
∗
Bits
Input Bias Current
0.1
10
∗
∗
pA
Range Error Match(7)
All Ranges
0.1
0.5
∗
∗
% of FSR
Range Sensitivity to VREF
VREF = 4.096
± 0.1V
1:1
∗
Offset Error
±400
±1000
∗
∗
ppm of FSR
Offset Error Match(7)
±100
∗
ppm of FSR
DC Bias Voltage(9)
Low-Level Input (< 1% FSR)
±0.05
±2
∗
∗
mV
Power-Supply Rejection Ratio
at dc
±25
±200
∗
∗
ppm of FSR/V
Internal Test Signal
11
∗
pC
Internal Test Accuracy
±10
∗
%
PERFORMANCE OVER TEMPERATURE
Offset Drift
±0.5
±3(8)
∗
∗
ppm of
FSR/
°C
Offset Drift Stability
±0.2
±1(8)
∗
∗
ppm of FSR/
minute
DC Bias Voltage Drift(9)
3
∗
µV/°C
Input Bias Current Drift
TA = +25
°C to +45°C
0.01
1(8)
∗
∗
pA/
°C
Range Drift(10)
25
∗
ppm/
°C
REFERENCE
Voltage
4.000
4.096
4.200
∗
∗
∗
V
Input Current(11)
Average Value
75
95
µA
(1)
∗ indicates that specification is the same as Low-Power Mode.
(2) Exceeding maximum input current specification may damage device.
(3) Input is less than 1% of full scale.
(4) CSENSOR is the capacitance seen at the DDC114 inputs from wiring, photodiode, etc.
(5) FSR is Full-Scale Range.
(6) A best-fit line is used in measuring nonlinearity.
(7) Matching between side A and side B of the same input.
(8) Ensured by design, not production tested.
(9) Voltage produced by the DDC114 at its input which is applied to the sensor.
(10)Range drift does not include external reference drift.
(11)Input reference current decreases with increasing TINT (see the Voltage Reference section, page 11).



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