DDC114IRTCRG3 datasheet(13/37 Pages) TI1

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DDC114

SBAS255C − JUNE 2004 − REVISED APRIL 2009

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DIGITAL INTERFACE

The digital interface of the DDC114 provides the digital

results via a synchronous serial interface consisting of

differential data clocks (DCLK and DCLK), a valid data pin

(DVALID), differential serial data output pins (DOUT and

DOUT), and differential serial data input pins (DIN and

DIN). The DDC114 contains only two A/D converters, so

the conversion process is interleaved (see Figure 2,

page 8). The integration and conversion processes are

independent of the data retrieval process. Consequently,

the CLK frequency and DCLK frequencies need not be the

same. DIN and DIN are used when multiple converters are

cascaded. Cascading or daisy-chaining greatly simplifies

the interconnection and routing of the digital outputs in

cases where a large number of converters are needed.

Refer to the Cascading Multiple Converters section of this

data sheet for more detail.

Complementary Signals (DCLK, DIN, and DOUT)

The DDC114 provides optional complementary inputs

(DCLK, DIN) to help reduce digital coupling to the analog

inputs. If using these inputs, connect a complementary

signal to each. If these inputs are not connected on the

DDC114, they should be tied to DGND. DOUT is a

complementary output designed to drive DIN. If not using

DOUT, leave it floating.

System and Data Clocks (CLK and CONV)

The system clock is supplied to CLK and the data clock is

supplied to DCLK. Make sure the clock signals are

clean—avoid overshoot or ringing. For best performance,

generate both clocks from the same clock source. DCLK

should be disabled by taking it low after the data has been

shifted out or while CONV is transitioning.

When using multiple DDC114s, pay close attention to the

DCLK distribution on the printed circuit board (PCB). In

particular, make sure to minimize skew in the DCLK signal

as this can lead to timing violations in the serial interface

specifications. See the Cascading Multiple Converters

section for more details.

System Clock Divider (CLK_4X)

The CLK_4X input enables an internal divider on the

system clock as shown in Table 3. When CLK_4X = 1, the

system clock is divided by four. This allows a 4X faster

system clock, which in turn provides a finer quantization of

the integration time as the CONV signal needs to be

synchronized with the system clock for the best

performance.

Table 3. CLK_4X Pin Operation

CLK_4X

CLK DIVIDER

VALUE

CLK FREQUENCY

INTERNAL CLOCK

FREQUENCY

4MHz

16MHz

4MHz

High-Speed and Low-Power Modes

(HISPD/LOPWR)

The HISPD/LOPWR input controls the power dissipation

and in turn the maximum allowable CLK frequency and

data rate, as shown in Table 4. With HISPD/LOPWR = 0,

the Low-Power Mode is selected with a typical 13.5mW/

channel and a maximum data rate of 2.5kSPS. Setting

HISPD/LOPWR = 1 selects the High-Speed Mode, which

supports a maximum data rate of 3.125kSPS with a corre-

sponding typical power of 18.0mW/channel.

Table 4. HISPD/LOPWR Pin Operation

HISPD/

LOPWR

MODE

TYPICAL

POWER/

CHANNEL

MAXIMUM

CLK FREQUENCY

(CLK_4X = 0)

MAXIMUM

DATA

RATE

Low Power

13.5mW/ch

4.0MHz

2.5kSPS

High Speed

18.0mW/ch

4.8MHz

3.125kSPS

Data Valid (DVALID)

The DVALID signal indicates that data is ready. Data

retrieval may begin after DVALID goes low. This signal is

generated using an internal clock divided down from the

system clock CLK. The phase relationship between this

internal clock and CLK is set when power is first applied,

and is random. Since the user must synchronize CONV

with CLK, the DVALID signal will have a random phase

relationship with CONV. This uncertainty is

±1/fCLK. Polling

DVALID eliminates any concern about this relationship. If

data read back is timed from CONV, wait the maximum

value of t7 or t8 to insure data is valid.

Reset (RESET)

The DDC114 is reset asynchronously by taking the

RESET input low, as shown in Figure 9. Make sure the

reset pulse is at least 50

µs wide. After resetting the

DDC114, wait at least four conversions before using the

data. It is very important to make sure the RESET is glitch

free to avoid unintended resets. The RESET pin is used

during power-up; see the Power-Up Sequence section for

more details.

RESET

>50

µs

Figure 9. Reset Timing

Convert (CONV)

CONV controls the integration time (TINT). For optimum

analog performance, make sure CONV is synchronized to

CLK.

This recommendation implies that while SPEED is low,

TINT needs to be adjusted in steps of 250ns if CLK_4X is

low and CLK = 4MHz. If CLK_4X is high and CLK =

16MHz, this allows TINT to be adjusted in steps of 62.5ns.

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