DDC114IRTCRG3 datasheet(9/37 Pages) TI1

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DDC114

SBAS255C − JUNE 2004 − REVISED APRIL 2009

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The digital interface of the DDC114 provides the digital

results via a synchronous serial interface consisting of

differential data clocks (DCLK and DCLK), a valid data pin

(DVALID), differential serial data output pins (DOUT and

DOUT), and differential serial data input pins (DIN and

DIN). The DDC114 contains only two A/D converters, so

the conversion process is interleaved (see Figure 2). The

integration and conversion process is fundamentally

independent of the data retrieval process. Consequently,

the CLK frequency and DCLK frequencies need not be the

same. DIN and DIN are only used when multiple

converters are cascaded, and otherwise should both be

tied to DGND.

DEVICE OPERATION

Basic Integration Cycle

The topology of the front end of the DDC114 is an analog

integrator, as shown in Figure 3. In this diagram, only Input

IN1 is shown. This representation of the input stage

consists of an operational amplifier, a selectable feedback

capacitor network (CF), and several switches that

implement the integration cycle. The timing relationships

of all of the switches shown in Figure 3 are illustrated in

Figure 4. Figure 4 is used to conceptualize the operation

of the integrator input stage of the DDC114 and should not

be used as an exact timing tool for design. See Figure 5 for

the block diagrams of the reset, integrate, wait and convert

states of the integrator section of the DDC114. This

internal switching network is controlled externally with the

convert

(CONV),

range

selection

pins

(RANGE0

−RANGE2), and the system clock (CLK). For

the best noise performance, CONV must be synchronized

with the rising edge of CLK. It is recommended that CONV

toggle within

±10ns of the rising edge of CLK.

The noninverting inputs of the integrators are connected to

ground. Consequently, the DDC114 analog ground should

be as clean as possible. The range switches, along with

the internal and external capacitors (CF), are shown in

parallel between the inverting input and output of the

operational amplifier. At the beginning of a conversion, the

switches SA/D, SINTA, SINTB, SREF1, SREF2, and SRESET are

set (see Figure 4).

50pF

25pF

12.5pF

VREF

RANGE2

RANGE1

RANGE0

To Converter

RESET

REF2

A/D1A

INTA

REF1

INTB

IN1

ESD

Protection

Diodes

Input

Current

Integrator A

Integrator B (same as A)

Photodiode

3pF

Figure 3. Basic Integration Configuration for Input 1, Shown with a 250pC (CF = 62.5pF) Input Range

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