SFDR

dBc

-

50

55

60

65

75

80

85

90

10

100

200

70

300

400

500

600

85

85

80

80

80

80

77

77

77

77

77

73

73

73

70

70

70

65

65

65

60

80

85

85

85

85

f

InputFrequency

MHz

-

400

350

300

250

200

150

100

40

ADS5474

SLAS525B

– JULY 2007 – REVISED FEBRUARY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

=

–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.

SFDR

vs

INPUT FREQUENCY AND SAMPLING FREQUENCY

Figure 30.

APPLICATIONS INFORMATION

Theory of Operation

The ADS5474 is a 14-bit, 400-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and

3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion

process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is

captured by the input track-and-hold (T

&H), and the input sample is converted sequentially by a series of lower

resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in

a data latency of 3.5 clock cycles, after which the output data are available as a 14-bit parallel word, coded in

offset binary format.

Input Configuration

The analog input for the ADS5474 consists of an analog pseudo-differential buffer followed by a bipolar transistor

T

&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents

a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input.

The input common-mode is set internally through a 500-

Ω resistor connected from 3.1 V to each of the inputs

(common-mode is ~2.4V on 12- and 13-bit members of this family). This configuration results in a differential

input impedance of 1 k

Ω.

18

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