Thisisanexampleblockdiagram.

Low-JitterClockDistribution

ADC

ADS5474

VCXO

REF

CDC

(ClockDistributionChip)

CDCM7005

800MHz(totransmitDAC)

100MHz(toDSP)

200MHz(toFPGA)

ToOther

BoardMaster

ReferenceClock

(highorlowjitter)

10MHz

400MHz

Low-JitterOscillator

800MHz

BPF

LVCMOS

LVPECL

or

LVCMOS

XFMR

AMP

CLKIN

CLKIN

AMPand/orBPFareOptional

ADS5474

www.ti.com

SLAS525B

– JULY 2007 – REVISED FEBRUARY 2012

Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI

CDC7005, the CDCM7005 and CDCE72010. Depending on the jitter requirements, a band pass filter (BPF) is

sometimes required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude

to be too low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be

placed between the CDC and the BPF.

Figure 47 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005 with

the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might

generally be well-suited for use with greater than 150 MHz of input frequency. The jitter of this setup is difficult to

estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost

amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter

provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends largely on the phase

noise of the VCXO selected, as well as the CDCM7005, and typically has 50

–100 fs of rms jitter. If it is

determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible

to clock the ADS5474 directly from the CDCM7005 using differential LVPECL outputs, as illustrated in Figure 48

(see the CDCM7005 data sheet for the exact schematic). This scenario may be more suitable for less than 150

MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter is recommended

before determining the proper approach.

Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output

frequency and amplitude ranges.

Figure 47. Optimum Jitter Clock Circuit

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© 2007–2012, Texas Instruments Incorporated

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