ML7406 datasheet(40/104 Pages) ETC2

40 / 104 page

FEDL7406-02

ML7406

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(Note)

1. If reading FIFO data is terminated before reading all data, STATE_CLR1 [STATE_CLR: B0 0x16(1)] (RX FIFO

pointer clear) must be issued. Otherwise If RX_FIFO is not cleared, the pointer controlling FIFO data keeps the same

status. Next RX data will not be processed in the FIFO properly.

For example, when RX_FIFO access error interrupt (INT[12] group2) is generated. This interrupt occurs when

RX_FIFO overrun (data received when no space in RX_FIFO) or underrun (reading empty RX_FIFO).

2. If 1 packet data is kept in the RX_FIFO, next RX data will be overwritten.

IF TX/RX pack is larger than FIFO size, FIFO access can be controlled by FIFO-Full trigger or FIFO-Empty trigger.

(1) TX FIFO usage notification function

This function is to notice TX_FIFO usage to the MCU using interrupt (SINTN). If TX_FIFO usage (un-transmitted data in

TX_FIFO) exceed the Full level threshold set by [TXFIFO_THRH: B0 0x17] register, interrupt will generate as FIFO-full

interrupt (INT[5] group1). If TX_FIFO usage is smaller than Empty level threshold set by [TXFIFO_THRL: B0 0x18] register,

FIFO-Empty interrupt will generate as FIFO-Empty interrout (INT[4] grou1). Interrupt signal (SINTN) can be output from

GPIO* or EXT_CLK pin.

For output setting, please refer to [GPIO1_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0 0x50],

[GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52] registers for output setting.

(Reference Sequence)

Set Full level threshold and Empy level threshold..Each threshold should set as TXFIFO_THRH[5:0]

([TXFIFO_THRH:B0 0x17(5-0)]) > TXFIFO_THRL[5:0] ([TXFIFO_THRL:B0 0x18(5-0)]). And enabling Full level

threshold by TXFIFO_THRH_EN([TXFIFO_THRH:B0 0x17(7)=0b1.

Enabling FAST_TX mode by FAST_TX_EN([RF_STATUS_CTRL:B0 0x0A(5)])=0b1 and start writing TX data to the

TX_FIFO[WR_TX_FIFO:B0 0x7C] until FIFO-Full interrupt (INT[5] group1) occurs.

After FIFO-Full interrupt is generated, Clear the interupt. Then disabling Full level threshold (TXFIFO_THRH_EN=

0b0) and enabling Empty level threshold (TXFIFO_THRL_EN([TXFIFO_THRL:B0 0x18(7)])=0b1).

After FIFO-Empty interrupt (INT[4] group1) is generated, Clear the interupt. Then disabling Empty level threshold

(TXFIFO_THRL_EN=0b0) and enabling Full level threshold (TXFIFO_THRH_ EN=0b1). Then resume writing TX

data to the TX_FIFO until next FIFO-Full interrupt occurs.

Repeat 3.-4. until completion of TX.

Empty level

(Example 0x0F)

Full level

(Example 0x2E)

0x3F

Generate interrupt

when TX data usage

is smaller than

Empty level

[FIFO usage]

Time

Full level

Empty level

TX data amount

TX_FIFO usage transition

0x0F

0x2E

SINTN signal

TX start timing by

FAST_TX trigger

Clear interrupt

0x00

Generate interrupt

when written Data

exceed Full level

ML7406 Datasheet(PDF) 40 Page - List of Unclassifed Manufacturers

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