ML7406 datasheet(80/104 Pages) ETC2

80 / 104 page

FEDL7406-02

ML7406

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(2) Interrupt generation timing

In each interrupt generation, timing from reference point to interrupt generation (notification) are described in the following

table. Timeout procedure for interrupt notification waiting are also described below.

(Note)

(1)The values are described in units of “bit cycle” in the below tablee is the value at 100kbps. If using other data rate,, please

esitimate with appropriate “bit cycle”.

(2)Below table uses the following format for TX/RX data.

10 byte

2 byte

1 byte

24 byte

2byte

Preamble

SyncWord

Length

User data

CRC

(3)Even if each interrupt notification is masked, in case of interrupt occurence, interrupt elements are stored internally.

Therefore, as soon as interrupt notification is unmasked, interrupt will generate.

Interrupt notice

Reference point

Timing From reference point to interrupt generation

or interrupt generation timing

RESETN release

(upon power-up)

50μs

INT[0]

CLK stabilization

completion

SLEEP release

(recovered from

SLEEP)

50μs

VCO calibration

completion

VCO calibration

start

230μs

INT[1]

FUSE access completion

RESETN release

48μs

INT[2]

PLL unlock detection

(TX) during TX after PA enable.

(RX) during RX enable after RX enable.

TX_ON command

(IDLE) 210μs

(RX) 192μs

RX_ON command

(IDLE) 119μs

(RX) 244μs

TRX_OFF

command

(TX) 147μs

(RX) 4μs

INT[3]

RF state transition

completion

Force_TRX_OFF

Command

(TX) 147μs

(RX) 4μs

(TX)

TX_ON command

(*1)

NRZ coding, Empty trigger level is set to 0x02.

RFwake-up(210μs)+35byte(preamble to 22

nd Data byte) ×8bit ×

10(bit cycle) =3010μs

INT[4]

FIFO-Empty detection

(RX) -

By FIFO read, remaining FIFO data is under trigger level

(TX) -

By FIFO write, FIFO usage exceed trigger level

INT[5]

FIFO-Full detection

(RX)

SyncWord detection

NRZ coding, Full trigger level is set to 0x05.

6byte (Length to 5

th Data byte) ×8bit ×10μs(bit cycle) = 480μs

INT[6]

Wake-up timer

completion

SLEEP setting

Wake-up timer is completed.

For details, please refer to “wake-up timer”

INT[7]

Clock calibration

completion

Calibration start

Calibration timer is completed.

For details, please refer to “low speed clock shift detection

function”.

INT[8]

RX completion

SyncWord detection

NRZ coding

27byte (L-ength to CRC) ×8bite ×10(bit cycle)=2160μs

INT[9]

CRC error detection

SyncWord detection

(Format A/B) each RX CRC block calculation completion

(Format C) RX completion

INT[10]

Diversity search

completion

SyncWord detection during diversity enable setting

INT[11]

RX Length error

detection

SyncWord detection

80μs (L-field 1byte)

160μs (L-field 2byte)

INT[12]

RX FIFO access error

detection

(1)overflow occurs because FIFO read is too slow.

(2)underflow occurs because too many FIFO data is read

INT[13]

SyncWord detection

INT[14]

Field check completion

Match or mismatch detected in Field check

(*1) Before issuing TX_ON, writing full length TX data to the TX_FIFO.

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