ML7406 datasheet(69/104 Pages) ETC2

69 / 104 page

FEDL7406-02

ML7406

69/104

The follwing is timing chart for IDLE detection.

[Upon BUSYdetection, continue CCA and IDLE detection case]

(Note)

*1 During CCA operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by

setting CCA_MASK_EN([CCA_MASK_SET: B2 0x7E(4)]) = 0b1. Stabilization time should be 1 ADC conversion time.

If this register is enabled, input operation is suspended until filter become stable.

[Condition]

ADC_CK_SEL([ADC_CLK_SET: B0 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0]([ED_CTRL: B0 0x41(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0] ([IDLE_WAIT_L/H: B0 0x3C/3B(1-0)])=0b00_0000_0000 (IDLE detection period 0μs)

(21-28)

(22-29)

ED value average period

0b10(CCA on-going)

ED0

ED7

ED8

ED28

0b00(IDLE)

INVALID

averaging

CCA execution period(Min.128μs+IDLE detection period)

IDLE detection period

(20-27)

> CCA_LVL

B0 0x37

(0-7)

(1-8)

ED27

ED29

<CCA_LVL

B0 0x37

BUSY INT. not generated

0b01(BUSY)

After IDLE detection, CCA will be completed,

then CCA_EN, CCA_IDLE_EN are reset to

0b0 automatically..

ED value

(internal signal)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_IDLE_EN/CCA_EN

[CCA_CTRL: B0 0x39(6/4)]

AD conversion

(16μs)

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period

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