ML7406 datasheet(52/104 Pages) ETC2

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FEDL7406-02

ML7406

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●Frequency Setting Function

○Channel frequency setting

Maximum 256 channels can be selected (CH#0 -CH#255) by the following resisters.

Frequency

[TXFREQ_I: B1 0x1B], [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D] and [TXFREQ_FL:

B1 0x1E]

CH#0 frequency

[RXFREQ_I: B1 0x1F], [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21] and [RXFREQ_FL:

B1 0x22]

Channel space

[CH_SPACE_H: B1 0x23] and [CH_SPACE_L: B1 0x24]

Channel setting

[CH_SET: B0 0x09]

(1) Channel frequency setting overview

[Channel frequency setting]

Using above registers, channel frequency is defined as following formula.

Channel frequency = i) CH#0 frequency + ii) channel space * iii) channel setting

[Channel frequency allocation image]

(Note)

The channel frequency to be selected must meet the following conditions. If the following conditions cannot be met,

please change channel #0 frequency or use other channels. If this formula cannot be met, expected frequency is not

functional or PLL may not be locked.

TX: (FMCK1*n + 500kHz ) ≤ channel frequency ≤ (FMCK1*(n+1) – 500kHz )

RX: (FMCK1*n +2.2MHz ) ≤ channel frequency ≤ (FMCK1*(n+1) )

FMCK1: Master clock frequency

n = integer

Unusable Frequency

Usable Frequency

(FMCK1×n )

Frequency

(FMCK1×(n+1))

Frequency

ii) channel space setting

i) CH#0 frequency setting

Channel No.

···

255

iii) channel setting

(setting Nth channel)

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