ML7406 datasheet(71/104 Pages) ETC2

71 / 104 page

FEDL7406-02

ML7406

71/104

The follwing is timing chart for CCA determination exclusion under strong signal.

[During IDLE_WAIT counting, detected extremly strong signal. After the given signal is out of averaging target, IDLE

detection case]

ED7

INVALID

(0-7)

(1-8)

(6-13)

ED8

ED13

ED14

0x001

0x006

0b11(on-going)

0x000

(14-21)

(7-14)

ED value>CCA_IGNORE_LVL

detection and reset

Due to extreme strong signal detection,

CCA_RSLT is not indicating IDLE.

CCA_RSLT=0b11 do not generate interrupt

ED15

(8-15)

ED21

(22-29)

ED22

(15-22)

0x007

ED29

0b00(IDLE)

Resume counting due to the extreme

strong signal is out of averaging target.

CCA _RSLT maintains until

IDLE/BUSY detected.

ED VALUE>CCA_IGNORE_LVL

ED value <CCA_IGNORE_LVL

Average ED value <CCA_LEVEL

(If average ED value >CCA_LVL, then BUSY detection.)

0b10(on-going)

ED value

(internal signal)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_PROG[9:0]

[CCA_PROG_L/H:B0 0x3E/3D]

ED value<CCA_IGNORE_LVL

[Condition]

CCA normal mode

ADC_CK_SEL([ADC_CLK_SET: B0 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0]([ED_CTRL: B0 0x41(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0]([IDLE_WAIT_L/H: B0

0x3C/3B(1-0)])=0b00_0000_0111(IDLE detection period 112μs)

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