ML7406 datasheet(89/104 Pages) ETC2

89 / 104 page

FEDL7406-02

ML7406

89/104

VCO calibration is necessary every 0.6ms to 3.9ms.

After completion, capacitance compensation values are stored in the following registers.

Capacitance compensation value at low limit frequency: [VCAL_MIN: B1 0x52]

Capacitance compensation value at upper limit frequency: [VCAL_MAX: B1 0x53]

In actual operation, based on the 2 compensation values, the most optimized capacitance value for the frequency is

calculated and applied. The calculated value is stored in [VCO_CAL: B0 0x6E].

By evaluation stage, if below values are stored in the MCU memory and uses these values upon reset or power-up,

calibration operation can be omitted.

Registers to be saved in the MCU memory.

[VCO_CAL_MIN_I: B1 0x4D]

[VCO_CAL_MIN_FH: B1 0x4E]

[VCO_CAL_MIN_FM: B1 0x4F]

[VCO_CAL_MIN_FL: B1 0x50]]

[VCO_CAL_MAX_N: B1 0x51]

[VCAL_MIN: B1 0x52]

[VCAL_MAX: B1 0x53]

(Note)

1. For low limit frequency, please use frequency at least 2.2MHz lower than operation frequency.

2. Upper limit frequency should be selected so that operation frequency is in the frequency range.

3. In case of like a channel change, if the setting frequency is outside of calibration frequency range, calibration has to be

performed again with proper frequency.

4. If PLL unlock occures, PLL unlock interrupt (INT[02] group1) will geneate. The following shows the ML7406

opereation related with LSI state and PLL_LD_EN([PLL_LOCK_DETECT:B1 0x0B(7)]) setting, after interrupt

generation.

PLL lock detection control setting and ML7406 operation after interrupt generation

LSI

state

check timig of

PLL unlock detection

PLL_LD_EN=0b1

[PLL_LOCK_DETECT:B1 0x0B(7)]

PLL_LD_EN=0b0

[PLL_LOCK_DETECT:B1 0x0B(7)]

PA_ON =”H”

interrupt occurs and TX stops forcibly

interrupt occurs and TX is continued

RX enable =”H”

interrupt occurs and RX is continued

○VCO low limit frequency setting

VCO low limit frequency can be set as described in the “channel frequency setting”. I is set to [VCO_CAL_MIN_I:B0

0x4D] register, F is set to [VCO_CAL_MIN_FH:B0 0x4E], [VCO_CAL_MIN_FM:B0 0x4F], [VCO_CAL_MIN_FL:B0

0x50] registers in MSB – LSB order.

example) If operation low limit frequency is 870MHz, setting value should be lower than 2.2MHz, Then in following

example, low limit frequency is set to 866MHz, master clock frequency is 26MHz.

I = 866MHz/26MHz (Integer part) = 33(0x21)

F =(866MHz/26MHz-33)×2

20 (Integer part) = 12905550 (0xC4EC4E)

Setting values for each register is as follows:

[VCO_CAL_MIN_I]

= 0x21

[VCO_CAL_MIN_FH] = 0xC4

[VCO_CAL_MIN_FM] = 0xEC

[VCO_CAL_MIN_FL] = 0x4E

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