ML7406 datasheet(43/104 Pages) ETC2

43 / 104 page

FEDL7406-02

ML7406

43/104

Preamble can be set by PB_PAT([DATA_SET1: B0 0x07(7)] and TXPR_LEN[15:0] ([TXPR_LEN_H/L: B0 0x42/43]).

SyncWord can be set by SYNCWORD_SEL([DATA_SET1: B0 0x08(4)), SYNCWORD_LEN[5:0] ([SYNC_WORD_

LEN: 1 0x25(5-0)]), SYNC_WORD_EN* ([SYNC_WORD_EN: B1 0x26(3-0)]), SYNC_WORD1[31:0] ([SYNCWORD1_

SET3/2/1/0: B1 0x27/28/29/2A]), SYNC_WORD2[31:0] ([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E]).

[RX]

i) Continuous output mode (to host)

Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b01.

After RX_ON(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x6), DCLK is output continuously. RX data (demodulated

data) is output from DIO pin at falling edge of DCLK. RX data is not stored in RX_FIFO.

(Note) For details of timing, please refer to the “RX” in the “Timing Chart”.

ii) Data output mode 1 (to host)

Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)]) =0b10.

After SyncWord detection, RX data is buffered in RX_FIFO. RX data buffering will continue until RX sync signal

(SYNC) becomes ”L”. By setting DIO_START ([DIO_SET: B0 0x0C(0)])=0b1, top data of buffered data will be output

through DIO interface (DIO/DCLK). (RX data is output at falling edge of DCLK). However, if DIO_START setting is

done after 64 byte timing, the top byte will be over written. If all buffered data is output until SYNC becomes ”L”, RX

completion interrupt (INT[8] group 2) will be generated. After RX completion, ready to receive next packet.

(Note)

RX data buffering in RX_FIFO is accessed byte by byte. DIO_START should be issued after 1 byte access time upon SyncWord

detection.

This mode does not process L-field. Field checking function is not supported.

DIO(GPIO0-3,EXT_CLK)

RX_ON

command

RX data

DCLK(GPIO0-3,EXT_CLK)

Preamble

SyncWord

Data-field

TRX_OFF

command

DIO(GPIO0-3,EXT_CLK)

RX_ON

command

RX data

DCLK(GPIO0-3,EXT_CLK)

Preamble

SyncWord

Data-field

TRX_OFF

command

Buffering to RX_FIFO

RX sync signal

DIO_START =0b1

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