HT82K68 datasheet(14/40 Pages) HOLTEK

14 / 40 page

HT82K68E

August 8, 2000

Preliminary

cuted to clear the WDT; otherwise, the WDT may

reset the chip because of the time-out.

Power down operation - HALT

The HALT mode is initialized by the HALT in-

struction and results in the following...

· The system oscillator will turn off but the

WDT oscillator keeps running (if the WDT os-

cillator is selected).

· The contents of the on chip RAM and regis-

ters remain unchanged.

· WDT and WDT prescaler will be cleared and

recount again (if the WDT clock has come

from the WDT oscillator).

· All I/O ports maintain their original status.

· The PD flag is set and the TO flag is cleared.

The system can leave the HALT mode by means

of an external reset, an external falling edge

signal on port A and port C [0:3] or a WDT over-

flow. An external reset causes a device initializa-

tion and the WDT overflow performs a ²warm

reset². Examining the TO and PD flags, the rea-

son for chip reset can be determined. The PD flag

is cleared when system power-up or executing the

CLR WDT instruction and is set when the HALT

instruction is executed. The TO flag is set if the

WDT time-out occurs, and causes a wake-up that

only resets the PC and SP, the others keep their

original status.

The port A or port C [0:3] wake-up can be con-

sidered as a continuation of normal execution.

Each bit in port A can be independently se-

lected to wake up the device by mask option.

Awakening from an I/O port stimulus, the pro-

gram will resume execution of the next instruc-

tion.

Once a wake-up event occurs, and the system

clock comes from a crystal, it takes 1024 tSYS

(system clock period) to resume normal opera-

tion. In other words, the HT82K68E will insert

a dummy period after the wake-up. If the sys-

tem clock comes from an RC oscillator, it contin-

ues operating immediately. If the wake-up

results in next instruction execution, this will

execute immediately after the dummy period is

completed.

To minimize power consumption, all I/O pins

should be carefully managed before entering

the HALT status.

Reset

There are three ways in which a reset can occur:

· RESET reset during normal operation

· RESET reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different

from other chip reset conditions, since it can

perform a warm reset that just resets the PC

and SP, leaving the other circuits to remain in

their original state. Some registers remain un-

changed during other reset conditions. Most

registers are reset to the ²initial condition²

S yst e m c l o ck/ 4

8- bi t C ount e r

W D T P r e sca l e r

7- bi t C ount e r

8- t o - 1 M U X

W D T T i m e - out

WS 0 ~ WS 2

RO M

C ode

Op t i o n

Se l e c t

WD T

OS C

Watchdog Timer

RE S E T

VD D

S S T Ti m e - o u t

C h i p R es et

t SS T

Reset timing chart

HT82K68 Datasheet(PDF) 14 Page - Holtek Semiconductor Inc

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