HDMP-1024 datasheet(36/40 Pages) HP

36 / 40 page

651

Double Frame Mode

(MDFSEL=1)

A block diagram showing the

double-frame mode data interface

for both the Tx and Rx, and their

associated timing diagrams are

shown in Figure 17. This

configuration works best if the

duty cycle of STRBIN is 50%.

In the Tx side, the expected

frequency is 1/2 of the combined

frame period. This combined

frame, D0-D19, is formed by

interlacing the two frames C0-

C19 and C20-C39 with an

external 2:1 multiplexer. The Tx

locks onto STRBIN, which has the

same frequency as the bit rate of

C0-C39, and with an internal

frequency doubler, generates the

sampling clock to latch in

D0-D19, DAV*, CAV*, and FLAG.

STRBIN is also used to toggle the

2:1 multiplexer, and is fed into

the flag input to signify the two

frames. The setup and hold times

are referenced to 1/2 frame

period of D0-D19, or 90 deg,

from the edges of STRBIN. The

multiplexer delay, tmux, should be

considered for timing margins.

The STRBOUT is derived from the

internal sampling clock, and thus

has a frequency double that of

STRBIN. The falling edge of

STRBOUT appears after the rising

and falling edges of STRBIN after

a delay of Tstrb. Other interlacing

techniques can also be achieved

with edge-triggered latches for

improved timing margins.

In the Rx side, the frame D0-D19

are demultiplexed back to the

original C0-C19, and C20-C39

frames with the use of external

edge-triggered flip-flops. The

toggle clock of the flip-flops,

RCLK, is derived by the state of

the FLAG bit. RCLK toggle with

the rising edge of STRBOUT with

a delay of tda. The two frames

appear with the rising and falling

edges of RCLK with a delay of tdb.

All of the synchronous outputs

and state machine outputs appear

after the falling edge of STRBOUT

with delays of td1 and td2

respectively.

The lower frame of C0-C19 can

be delayed further with additional

latches so that both C0-C19 and

C20-C39 frames are synchronous.

Figure 19. Transmitter and Receiver Data Interface and Timing for Double Frame Mode (MDFSEL=0).

CONFIGURATIONS

CAV*, DAV*

PLL

C00 - C19

STRBOUT

STRBIN

CONFIGURATIONS

CAV*, DAV*, FF

LINKRDY, ERROR

C00 - C19

STRBOUT

STAT0; STAT1

tstrb

CAV*, DAV*

STRBOUT

STRBIN

FLAG

CAV*, DAV*

FF, LINKRDY

ERROR

D00 - D19

STRBOUT

td1

ts = SETUP TIME

th = HOLD TIME

tstrb = STRBIN TO STRBOUT DELAY

tmux = 2:1 MULTIPLEXER DELAY

td1 = STRBOUT TO SYNCHRONOUS OUTPUTS DELAY

td2 = STRBOUT TO STATE MACHINE OUTPUTS DELAY

tda = STRBOUT TO RCLK DELAY

tdb = RCLK TO C00-C39 OUTPUT DELAY

2:1

MUX

D00 - D19

C20 - C39

D00 - D19

FLAG

1/2 FRAME

PERIOD

1/2 FRAME

PERIOD

D00 - D19

C00 - C19

C20 - C39

C00 - C19

C20 - C39

tmux

td2

STAT0

STAT1

FLAG

RCLK

C00 - C19

C20 - C39

C00 - C19

C20 - C39

tda

tdb

RCLK

HDMP-1024 Datasheet(PDF) 36 Page - Agilent(Hewlett-Packard)

HDMP-1024 Datasheet(HTML) 36 Page - Agilent(Hewlett-Packard)

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