HDMP-1024 datasheet(9/40 Pages) HP

9 / 40 page

624

HDMP-1022 (Tx) Timing

Figure 6 shows the Tx timing

diagram. Under normal

operations, the Tx PLL locks an

internally generated clock to the

incoming STRBIN. The incoming

data, D0-D19, ED, FF, DAV*,

CAV*, and FLAG, are latched by

this internal clock. For

MDFSEL=0, the input rate of

STRBIN is expected to be the

same as the parallel data rate. For

MDFSEL=1, STRBIN should be

1/2 of the incoming parallel data

rate. The data must be valid

before it’s sampled for a set-up

time (ts), and remain valid after

it’s sampled for a hold time (th).

In single frame mode

(MDFSEL=0), ts and th are

referenced to the rising edge of

STRBIN. In double frame mode

(MDFSEL=1), ts and th are

referenced to half the frame

period from the rising or falling

edge of STRBIN plus 4 ns.

STRBOUT appears after this

reference with a delay of

∆T

strb.

The rate of STRBOUT is always

the same as the word rate of the

incoming data, independent of

MDFSEL.

The start of a frame, D0, in the

high speed serial output occurs

after a delay of td after the rising

edge of the STRBIN. The typical

value of td may be calculated by

using the following formula.

Figure 6. HDMP-1022 (Tx) Timing Diagram.

HDMP-1022 (Tx) Timing Characteristics

Tc = 0

°C to +85°C, V

CC = 4.5 V to 5.5 V

Symbol

Parameter

Units

Min.

Typ.

Max.

Setup Time, for D0-D19 Relative to Rising Edge of STRBIN,

nsec

2.0*

ED, FF, DAV*, CAV* and FLAG

Hold Time, for D0-D19 Relative to Rising Edge of STRBIN,

nsec

2.0*

ED, FF, DAV*, CAV* and FLAG

∆T

strb

STRBOUT - STRBIN Delay at 64 MHz in 20-bit Mode

nsec

4.0

*In double frame mode, due to the internal clock delay, ts and th are referenced to half the frame period plus 4 ns from the rising or

falling edge of STRBIN.

1/2 FRAME PERIOD

tstrb

D-FIELD

C-FIELD

STRBIN

MDFSEL = 0

STRBIN

MDFSEL = 1

D00 - D19

ED, FF

DAV*, CAV*

FLAG

STRBOUT

DOUT

HCLK

HDMP-1024 Datasheet(PDF) 9 Page - Agilent(Hewlett-Packard)

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