GMS81608PL datasheet(44/79 Pages) HYNIX

44 / 79 page

BRK Interrupt

Software interrupt can be invoked by BRK instruction,

which is the lowest priority order.

Interrupt vector address of BRK is shared with the

vector of TCALL0 (Refer to Program Memory Sec-

tion). When BRK interrupt is generated, B-flag of

PSW is set to distinguish BRK from TCALL0.

Each processing step is determined by B-flag as shown

below.

Multiple Interrupt

If two requests of different priority levels are received

simultaneously, the request of higher priority level is

serviced. If requests of the same priority level are

received simultaneously, an internal polling sequence

determines by hardware which request is serviced.

Hardware interrupt priority is shown in Page37.

However, multiple processing through software for

special features is possible. Generally when an inter-

rupt is accepted, the I-flag is cleared to disable any

further interrupt. But as user set I-flag in interrupt

routine, some further interrupt can be serviced even if

certain interrupt is in progress.

B-FLAG

RETI

BRK or

TCALL0

BRK

INTERRUPT

ROUTINE

TCALL0

ROUTINE

RET

= 0

= 1

Figure 33. Execution of BRK/ TCALL0

MOV

IENH,#80H

MOV

IENL,#00H

RETI

Occur

TIMER 0 INTERRUPT

INT0

ROUTINE

RETI

MAIN

ROUTINE

TIMER 0

ROUTINE

MOV

IENH,#FFH

MOV

IENL,#FFH

INT 0

ROUTINE

In this example, the INT0 interrupt can be serviced without any

pending, even TIMER 0 is in progress.

Because of re-setting the interrupt enable registers IENH, IENL

and master enable flag "EI" in the Timer/Counter 0 routine.

Figure 34. Execution of Multi-Interrupt

GMS81604/08

LG Semicon

GMS81608PL Datasheet(PDF) 44 Page - Hynix Semiconductor

GMS81608PL Datasheet(HTML) 44 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL