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80188 Datasheet(PDF) 17 Page - Intel Corporation |
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80188 Datasheet(HTML) 17 Page - Intel Corporation |
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17 / 33 page  8018680188 AC CHARACTERISTICS (TA e 0 Cto a70 C VCC e 5V g10%) (Continued) Master Interface Timing Responses (Continued) Symbol Parameter 8 MHz 10 MHz Units Conditions Test Min Max Min Max TAZRL Address Float to RD Active 0 0 ns TCLRL RD Active Delay 10 70 10 56 ns TCLRH RD Inactive Delay 10 55 10 44 ns TRHAV RD Inactive to Address TCLCLb40 TCLCLb40 ns Active TCLHAV HLDA Valid Delay 5 50 5 40 ns TRLRH RD Width 2TCLCLb50 2TCLCLb46 ns TWLWH WR Width 2TCLCLb40 2TCLCLb34 ns TAVLL Address Valid to ALE Low TCLCHb25 TCLCHb19 ns TCHSV Status Active Delay 10 55 10 45 ns TCLSH Status Inactive Delay 10 65 10 50 ns TCLTMV Timer Output Delay 60 48 ns 100 pF max 810MHz TCLRO Reset Delay 60 48 ns TCHQSV Queue Status Delay 35 28 ns TCHDX Status Hold Time 10 10 ns TAVCH Address Valid to Clock High 10 10 ns TCLLV LOCK ValidInvalid Delay 5 65 5 60 ns Chip-Select Timing Responses TCLCSV Chip-Select Active Delay 66 45 ns TCXCSX Chip-Select Hold from 35 35 ns Command Inactive TCHCSX Chip-Select Inactive Delay 5 35 5 32 ns CLKIN Requirements TCKIN CLKIN Period 625 250 50 250 ns TCKHL CLKIN Fall Time 10 10 ns 35 to 10V TCKLH CLKIN Rise Time 10 10 ns 10 to 35V TCLCK CLKIN Low Time 25 20 ns 15V TCHCK CLKIN High Time 25 20 ns 15V CLKOUT Timing (200 pF load) TCICO CLKIN to CLKOUT Skew 50 25 ns TCLCL CLKOUT Period 125 500 100 500 ns TCLCH CLKOUT Low Time TCLCLb75 TCLCLb60 ns 15V TCHCL CLKOUT High Time TCLCLb75 TCLCLb60 ns 15V TCH1CH2 CLKOUT Rise Time 15 12 ns 10 to 35V TCL2CL1 CLKOUT Fall Time 15 12 ns 35 to 10V 17 17 |
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