80188 datasheet(7/33 Pages) INTEL

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8018680188

Table 1 Pin Descriptions

(Continued)

Symbol

Type

Name and Function

RD QSMD

Read Strobe is an active LOW signal which indicates that the processor is

performing a memory or IO read cycle It is guaranteed not to go LOW

before the AD bus is floated An internal pull-up ensures that RD is HIGH

during RESET Following RESET the pin is sampled to determine whether

the processor is to provide ALE RD and WR or queue status information

To enable Queue Status Mode RD must be connected to GND RD will

float during bus HOLD

ARDY

Asynchronous Ready informs the processor that the addressed memory

space or IO device will complete a data transfer The ARDY pin accepts a

rising edge that is asynchronous to CLKOUT and is active HIGH The

falling edge of ARDY must be synchronized to the processor clock

Connecting ARDY HIGH will always assert the ready condition to the CPU

If this line is unused it should be tied LOW to yield control to the SRDY pin

SRDY

Synchronous Ready informs the processor that the addressed memory

space or IO device will complete a data transfer The SRDY pin accepts an

active-HIGH input synchronized to CLKOUT The use of SRDY allows a

relaxed system timing over ARDY This is accomplished by elimination of

the one-half clock cycle required to internally synchronize the ARDY input

signal Connecting SRDY high will always assert the ready condition to the

CPU If this line is unused it should be tied LOW to yield control to the

ARDY pin

LOCK

LOCK output indicates that other system bus masters are not to gain

control of the system bus while LOCK is active LOW The LOCK signal is

requested by the LOCK prefix instruction and is activated at the beginning

of the first data cycle associated with the instruction following the LOCK

prefix It remains active until the completion of that instruction No

instruction prefetching will occur while LOCK is asserted When executing

more than one LOCK instruction always make sure there are 6 bytes of

code between the end of the first LOCK instruction and the start of the

second LOCK instruction LOCK is driven HIGH for one clock during RESET

and then floated

Bus cycle status S0 –S2 are encoded to provide bus-transaction

information

Bus Cycle Status Information

Bus Cycle Initiated

Interrupt Acknowledge

Read IO

Write IO

Halt

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (no bus cycle)

The status pins float during HOLD

S2 may be used as a logical MIO indicator and S1 as a DTR indicator

NOTE

Pin names in parentheses apply to the 80188

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