80188 datasheet(5/33 Pages) INTEL

5 / 33 page

8018680188

Table 1 Pin Descriptions

Symbol

Type

Name and Function

VCC

SYSTEM POWER a

5 volt power supply

VSS

System Ground

RESET

Reset Output indicates that the CPU is being reset and can be used as a system

reset It is active HIGH synchronized with the processor clock and lasts an

integer number of clock periods corresponding to the length of the RES signal

Crystal Inputs X1 and X2 provide external connections for a fundamental mode

parallel resonant crystal for the internal oscillator Instead of using a crystal an

external clock may be applied to X1 while minimizing stray capacitance on X2

The input or oscillator frequency is internally divided by two to generate the

clock signal (CLKOUT)

CLKOUT

Clock Output provides the system with a 50% duty cycle waveform All device

pin timings are specified relative to CLKOUT

RES

An active RES causes the processor to immediately terminate its present

activity clear the internal logic and enter a dormant state This signal may be

asynchronous to the processor clock The processor begins fetching

instructions approximately 6

clock cycles after RES is returned HIGH For

proper initialization VCC must be within specifications and the clock signal must

be stable for more than 4 clocks with RES held LOW RES is internally

synchronized This input is provided with a Schmitt-trigger to facilitate power-on

RES generation via an RC network

TEST

TEST is examined by the WAIT instruction If the TEST input is HIGH when

‘‘WAIT’’ execution begins instruction execution will suspend TEST will be

resampled until it goes LOW at which time execution will resume If interrupts

are enabled while the processor is waiting for TEST interrupts will be serviced

During power-up active RES is required to configure TEST as an input This pin

is synchronized internally

TMR IN 0

Timer Inputs are used either as clock or control signals depending upon the

programmed timer mode These inputs are active HIGH (or LOW-to-HIGH

TMR IN 1

transitions are counted) and internally synchronized

TMR OUT 0

Timer outputs are used to provide single pulse or continous waveform

generation depending upon the timer mode selected

TMR OUT 1

DRQ0

DMA Request is asserted HIGH by an external device when it is ready for DMA

Channel 0 or 1 to perform a transfer These signals are level-triggered and

DRQ1

internally synchronized

NMI

The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition

from LOW to HIGH is latched and synchronized internally and initiates the

interrupt at the next instruction boundary NMI must be asserted for at least one

clock The Non-Maskable Interrupt cannot be avoided by programming

INT0

Maskable Interrupt Requests can be requested by activating one of these pins

When configured as inputs these pins are active HIGH Interrupt Requests are

INT1SELECT

synchronized internally INT2 and INT3 may be configured to provide active-

INT2INTA0

LOW interrupt-acknowledge output signals All interrupt inputs may be

INT3INTA1 IRQ

configured to be either edge- or level-triggered To ensure recognition all

interrupt requests must remain active until the interrupt is acknowledged When

Slave Mode is selected the function of these pins changes (see Interrupt

Controller section of this data sheet)

NOTE

Pin names in parentheses apply to the 80188

80188 Datasheet(PDF) 5 Page - Intel Corporation

80188 Datasheet(HTML) 5 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL