80188 datasheet(6/33 Pages) INTEL

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8018680188

Table 1 Pin Descriptions

(Continued)

Symbol

Type

Name and Function

A19S6

Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most

significant address bits during T1 These signals are active HIGH During T2 T3 TW

A18S5

and T4 the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a

A17S4

DMA-initiated bus cycle During the same T-states S3 S4 and S5 are always LOW

A16S3

The status pins float during bus HOLD or RESET

AD15 (A15)

AddressData Bus signals constitute the time multiplexed memory or IO address (T1)

and data (T2 T3 TW and T4) bus The bus is active HIGH A0 is analogous to BHE for

AD14 (A14)

the lower byte of the data bus pins D7 through D0 It is LOW during T1 when a byte is

AD13 (A13)

to be transferred onto the lower portion of the bus in memory or IO operations BHE

AD12 (A12)

does not exist on the 80188 as the data bus is only 8 bits wide

AD11 (A11)

AD10 (A10)

AD9 (A9)

AD8 (A8)

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

BHE S7

During T1 the Bus High Enable signal should be used to determine if data is to be

enabled onto the most significant half of the data bus pins D15–D8 BHE is LOW

(S7)

during T1 for read write and interrupt acknowledge cycles when a byte is to be

transferred on the higher half of the bus The S7 status information is available during

T2 T3 and T4 S7 is logically equivalent to BHE BHE S7 floats during HOLD On the

80188 S7 is high during normal operation

BHE and A0 Encodings (80186 Only)

BHE

Function

Value

Word Transfer

Byte Transfer on upper half of data bus (D15–D8)

Byte Transfer on lower half of data bus (D7–D0)

Reserved

ALEQS0

Address Latch EnableQueue Status 0 is provided by the processor to latch the

address ALE is active HIGH Addresses are guaranteed to be valid on the trailing

edge of ALE The ALE rising edge is generated off the rising edge of the CLKOUT

immediately preceding T1 of the associated bus cycle effectively one-half clock cycle

earlier than in the 8086 The trailing edge is generated off the CLKOUT rising edge in

T1 as in the 8086 Note that ALE is never floated

WR QS1

Write StrobeQueue Status 1 indicates that the data on the bus is to be written into a

memory or an IO device WR is active for T2 T3 and TW of any write cycle It is active

LOW and floats during HOLD When the processor is in queue status mode the ALE

QS0 and WR QS1 pins provide information about processorinstruction queue

interaction

QS1

QS0

Queue Operation

No queue operation

First opcode byte fetched from the queue

Subsequent byte fetched from the queue

Empty the queue

NOTE

Pin names in parentheses apply to the 80188

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