80188 datasheet(26/33 Pages) INTEL

26 / 33 page

8018680188

EXECUTION TIMINGS

A determination of program execution timing must

consider the bus cycles necessary to prefetch in-

structions as well as the number of execution unit

cycles necessary to execute instructions The fol-

lowing instruction timings represent the minimum ex-

ecution time in clock cycles for each instruction The

timings given are based on the following assump-

tions

The opcode along with any data or displacement

required for execution of a particular instruction

has been prefetched and resides in the queue at

the time it is needed

No wait states or bus HOLDS occur

All word-data is located on even-address bound-

aries

All instructions which involve memory accesses can

also require one or two additional clocks above the

minimum timings shown due to the asynchronous

handshake between the bus interface unit (BIU) and

execution unit

All jumps and calls include the time required to fetch

the opcode of the next instruction at the destination

address

The 80186 has sufficient bus performance to ensure

that an adequate number of prefetched bytes will

reside in the queue (6 bytes) most of the time

Therefore actual program execution time will not be

substantially greater than that derived from adding

the instruction timings shown

The 80188 is noticeably limited in its performance

relative to the execution unit A sufficient number of

prefetched bytes may not reside in the prefetch

queue (4 bytes) much of the time Therefore actual

program execution time may be substantially greater

than that derived from adding the instruction timings

shown

80188 Datasheet(PDF) 26 Page - Intel Corporation