80C187 datasheet(9/30 Pages) INTEL

9 / 30 page

80C187

Table 5 Condition Code Defining Operand Class

Value at TOP

0000

Unsupported

0001

NaN

0010

Unsupported

0011

NaN

0100

Normal

0101

Infinity

0110

Normal

0111

Infinity

1000

1001

Empty

1010

1011

Empty

1100

Denormal

1111

Denormal

INSTRUCTION AND DATA POINTERS

Because the NPX operates in parallel with the CPU

any exceptions detected by the NPX may be report-

ed after the CPU has executed the ESC instruction

which caused it To allow identification of the failing

numerics instruction the 80C187 contains registers

that aid in diagnosis These registers supply the op-

code of the failing numerics instruction the address

of the instruction and the address of its numerics

memory operand (if appropriate)

The instruction and data pointers are provided for

user-written exception handlers

Whenever the

80C187 executes a new ESC instruction it saves

the address of the instruction (including any prefixes

that may be present) the address of the operand (if

present) and the opcode

The instruction and data pointers appear in the for-

mat shown by Figure 6

The ESC instruction

FLDENV FSTENV FSAVE and FRSTOR are used

to transfer these values between the registers and

memory Note that the value of the data pointer is

undefined if the prior ESC instruction did not have a

memory operand

Interrupt Description

CPU interrupt 16 is used to report exceptional condi-

tions while executing numeric programs Interrupt 16

indicates that the previous numerics instruction

caused an unmasked exception The address of the

faulty instruction and the address of its operand are

stored in the instruction pointer and data pointer reg-

isters Only ESC instructions can cause this inter-

rupt The CPU return address pushed onto the stack

of the exception handler points to an ESC instruction

(including prefixes) This instruction can be restarted

after clearing the exception condition in the NPX

FNINIT

FNCLEX

FNSTSW

FNSTENV

and

FNSAVE cannot cause this interrupt

Exception Handling

The 80C187 detects six different exception condi-

tions that can occur during instruction execution Ta-

ble 6 lists the exception conditions in order of prece-

dence showing for each the cause and the default

action taken by the 80C187 if the exception is

masked by its corresponding mask bit in the control

word

Any exception that is not masked by the control

word sets the corresponding exception flag of the

status word sets the ES bit of the status word and

asserts the ERROR signal When the CPU attempts

to execute another ESC instruction interrupt 16 oc-

curs The exception condition must be resolved via

an interrupt service routine The return address

pushed onto the CPU stack upon entry to the serv-

ice routine does not necessarily point to the failing

instruction nor to the following instruction

The

80C187 saves the address of the floating-point in-

struction that caused the exception and the address

of any memory operand required by that instruction

If error trapping is required at the end of a series of

numerics instructions (specifically when the last

ESC instruction modifies memory data and that data

is used in subsequent nonnumerics instructions) it is

necessary to insert the FNOP instruction to force the

80C187 to check its ERROR input

80C187 Datasheet(PDF) 9 Page - Intel Corporation

80C187 Datasheet(HTML) 9 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL