80C187 datasheet(18/30 Pages) INTEL

18 / 30 page

80C187

CPUNPX SYNCHRONIZATION

The pins BUSY PEREQ and ERROR are used for

various aspects of synchronization between the

CPU and the NPX

BUSY is used to synchronize instruction transfer

from the CPU to the 80C187 When the 80C187 rec-

ognizes an ESC instruction it asserts BUSY For

most ESC instructions

the CPU waits for the

80C187 to deassert BUSY before sending the new

opcode

The NPX uses the PEREQ pin of the CPU to signal

that the NPX is ready for data transfer to or from its

data FIFO The NPX does not directly access mem-

ory rather the CPU provides memory access serv-

ices for the NPX

Once the CPU initiates an 80C187 instruction that

has operands the CPU waits for PEREQ signals that

indicate when the 80C187 is ready for operand

transfer Once all operands have been transferred

(or if the instruction has no operands) the CPU con-

tinues program execution while the 80C187 exe-

cutes the ESC instruction

In 80868087 systems WAIT instructions are re-

quired to achieve synchronization of both com-

mands and operands The 80C187 however does

not require WAIT instructions The WAIT or FWAIT

instruction commonly inserted by high-level compil-

ers and assembly-language programmers for excep-

tion synchronization is not treated as an instruction

by the 80C186 and does not provide exception trap-

ping (Refer to the section ‘‘System Configuration for

8087-Compatible Exception Trapping’’)

Once it has started to execute a numerics instruction

and has transferred the operands from the CPU the

80C187 can process the instruction in parallel with

and independent of the host CPU When the NPX

detects an exception it asserts the ERROR signal

which causes a CPU interrupt

OPCODE INTERPRETATION

The CPU and the NPX use a bus protocol that

adapts to the numerics opcode being executed

Only the NPX directly interprets the opcode Some

of the results of this interpretation are relevant to the

CPU The NPX records these results (opcode status

information) in an internal 16-bit register

The

80C186 accesses this register only via reads from

NPX port 00FEH Tables 10 and 11 define the signal

combinations that correspond to each of the follow-

ing steps

1 The CPU writes the opcode to NPX port 00F8H

This write can occur even when the NPX is busy

or is signalling an exception The NPX does not

necessarily begin executing the opcode immedi-

ately

2 The CPU reads the opcode status information

from NPX port 00FEH

3 The CPU initiates subsequent bus cycles accord-

ing to the opcode status information The opcode

status information specifies whether to wait until

the NPX is not busy when to transfer exception

pointers to port 00FCH when to read or write op-

erands and results at port 00FAH etc

For most instructions the NPX does not start exe-

cuting the previously transferred opcode until the

CPU (guided by the opcode status information) first

writes exception pointer information to port 00FCH

of the NPX This protocol is completely transparent

to programmers

Bus Operation

With respect to bus interface the 80C187 is fully

asynchronous with the CPU even when it operates

from the same clock source as the CPU The CPU

initiates a bus cycle for the NPX by activating both

NPS1 and NPS2 the NPX select signals During the

CLK period in which NPS1 and NPS2 are activated

the 80C187 also examines the NPRD and NPRW

80C187 Datasheet(PDF) 18 Page - Intel Corporation

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