80C187 datasheet(15/30 Pages) INTEL

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80C187

Table 8 PLCC Pin Cross-Reference

Pin Name

CERDIP Package

PLCC Package

BUSY

CKM

CLK

CMD0

CMD1

D10

D11

D12

D13

D14

D15

ERROR

No Connect

6 11 23 33 40

NPRD

NPS1

NPS2

NPWR

PEREQ

RESET

VCC

3 9 13 37 40

1 3 10 15 42

VSS

1 4 10 30 36 38

2 4 12 34 41 43

System Reset (RESET)

A LOW to HIGH transition on this pin causes the

80C187 to terminate its present activity and to enter

a dormant state RESET must remain active (HIGH)

for at least four internal clock periods (The relation

of the internal clock period to CLK depends on

CLKM the internal clock may be different from that

of the CPU) Note that the 80C187 is active internal-

ly for 25 clock periods after the termination of the

RESET signal (the HIGH to LOW transition of RE-

SET) therefore the first instruction should not be

written to the 80C187 until 25 internal clocks after

the falling edge of RESET Table 9 shows the status

of the output pins during the reset sequence After a

reset all output pins return to their inactive states

Table 9 Output Pin Status during Reset

Output

Value

Pin Name

during Reset

BUSY

HIGH

ERROR

HIGH

PEREQ

LOW

D15–D0

TRI-STATE OFF

Processor Extension Request (PEREQ)

When active this pin signals to the CPU that the

80C187 is ready for data transfer tofrom its data

FIFO When there are more than five data transfers

80C187 Datasheet(PDF) 15 Page - Intel Corporation

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