80C187 datasheet(17/30 Pages) INTEL

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80C187

Table 10 Bus Cycles Definition

NPS1

NPS2

CMD0

CMD1

NPRD

NPWR

Bus Cycle Type

80C187 Not Selected

Opcode Write to 80C187

CW or SW Read from 80C187

Read Data from 80C187

Write Data to 80C187

Write Exception Pointers

Reserved

Read Opcode Status

Reserved

DATA INTERFACE AND CONTROL UNIT

The data interface and control unit latches the data

and subject to BCL control directs the data to the

FIFO or the instruction decoder The instruction de-

coder decodes the ESC instructions sent to it by the

CPU and generates controls that direct the data flow

in the FIFO It also triggers the microinstruction se-

quencer that controls execution of each instruction

If the ESC instruction is FINIT FCLEX FSTSW

FSTSW AX FSTCW FSETPM or FRSTPM the

control executes it independently of the FPU and the

sequencer The data interface and control unit is the

one that generates the BUSY PEREQ and ERROR

signals that synchronize 80C187 activities with the

CPU

FLOATING-POINT UNIT

The FPU executes all instructions that involve the

dental constant and data transfer instructions The

data path in the FPU is 84 bits wide (68 significant

bits 15 exponent bits and a sign bit) which allows

internal operand transfers to be performed at very

high speeds

Bus Cycles

The pins NPS1 NPS2 CMD0 CMD1 NPRD and

NPWR identify bus cycles for the NPX Table 10 de-

fines the types of 80C187 bus cycles

80C187 ADDRESSING

The NPS1 NPS2 CMD0 and CMD1 signals allow

the NPX to identify which bus cycles are intended for

the NPX The NPX responds to IO cycles when the

IO address is 00F8H 00FAH 00FCH or 00FEH

The correspondence betwen IO addresses and

control signals is defined by Table 11 To guarantee

correct operation of the NPX programs must not

perform any IO operations to these reserved port

addresses

Table 11 IO Address Decoding

IO Address

80C187 Select and Command Inputs

(Hexadecimal)

NPS2

NPS1

CMD1

CMD0

00F8

00FA

00FC

00FE

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