80C187 datasheet(19/30 Pages) INTEL

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80C187

input signals to determine whether the cycle is a

read or a write cycle and examines the CMD0 and

CMD1 inputs to determine whether an opcode oper-

and or controlstatus register transfer is to occur

The 80C187 activates its BUSY output some time

after the leading edge of the NPRD or NPRW signal

Input and ouput data are referenced to the trailing

edges of the NPRD and NPRW signals

The 80C187 activates the PEREQ signal when it is

ready for data transfer The 80C187 deactivates

PEREQ automatically

System Configuration

The 80C187 can be connected to the 80C186 CPU

as shown by Figure 9 (Refer to the 80C186 Data

Sheet for an explanation of the 80C186’s signals)

This interface has the following characteristics

The 80C187’s NPS1 ERROR PEREQ and

BUSY pins are connected directly to the corre-

sponding pins of the 80C186

The 80C186 pin MCS3 NPS is connected to

NPS1 NPS2 is connected to VCC Note that if the

80C186 CPU’s DEN signal is used to gate exter-

nal data buffers it must be combined with the

NPS signal to insure numeric accesses will not

activate these buffers

The NPRD and NPRW pins are connected to the

RD and WR pins of the 80C186

CMD1 and CMD0 come from the latched A2 and

A1 of the 80C186 respectively

The 80C187 BUSY output connects to the

80C186 TEST BUSY input During RESET the

signal at the 80C187 BUSY output automatically

programs the 80C186 to use the 80C187

The 80C187 can use the CLKOUT signal of the

80C186 to conserve board space when operating

at 125 MHz or less In this case the 80C187

CKM input must be pulled HIGH For operation in

excess of 125 MHz a double-frequency external

oscillator for CLK input is needed In this case

CKM must be pulled LOW

270640 – 7

Figure 9 80C18680C187 System Configuration

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