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82374EB Datasheet(PDF) 161 Page - Intel Corporation

Part # 82374EB
Description  SYSTEM COMPONENT (ESC)
PDF  208 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82374EB Datasheet(HTML) 161 Page - Intel Corporation

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82374EB82374SB
There are two ways to accomplish Automatic Rotation using OCW2 the Rotation on Non-Specific EOI Com-
mand (Re1 SLe0 EOIe1) and the Rotate in Automatic EOI Mode which is set by (Re1 SLe0 EOIe0)
and cleared by (Re0 SLe0 EOIe0)
964 SPECIFIC ROTATION (SPECIFIC PRIORITY)
The programmer can change priorities by programming the bottom priority and thus fixing all other priorities
For example if IRQ5 is programmed as the bottom priority device then IRQ6 will be the highest priority device
The Set Priority command is issued in OCW2 where Re1 SLe1 L0 – L2 is the binary priority level code of
the bottom priority device See the register description for the bit definitions
Note that in this mode internal status is updated by software control during OCW2 However it is independent
of the End of Interrupt (EOI) command (also executed by OCW2) Priority changes can be executed during an
EOI command by using the Rotate on Specific EOI command in OCW2 (Re1 SLe1 EOIe1 and L0 –
L2eIRQ level to receive bottom priority)
965 POLL COMMAND
The Polled Mode can be used to conserve space in the interrupt vector table Multiple interrupts that can be
serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll
command The Polled Mode can also be used to expand the number of interrupts The polling interrupt service
routine can call the appropriate service routine instead of providing the interrupt vectors in the vector Table In
this mode the INTR output is not used and the microprocessor internal Interrupt Enable flip-flop is reset
disabling its interrupt input Service to devices is achieved by software using a Poll command
The Poll command is issued by setting Pe1 in OCW3 The Interrupt Controller treats the next IO read pulse
to the Interrupt Controller as an interrupt acknowledge sets the appropriate IS bit if there is a request and
reads the priority level Interrupts are frozen from the IO write to the IO read The word enabled onto the
data bus during IO read is shown in Figure 22
290476 – 85
NOTES
1W0 – W2 Binary code of the highest priority level requesting service
2D 71 equal to 1 if there is an interrupt
Figure 22 Polled Mode
This mode is useful if there is a routine command common to several levels so that the INTA
sequence is
not needed (saves ROM space)
966 CASCADE MODE
The Interrupt Controllers in the ESC system are interconnected in a cascade configuration with one master
and one slave This configuration can handle up to 15 separate priority levels
The master controls the slaves through a three line internal cascade bus When the master drives 010b on the
cascade bus this bus acts like a chip select to the slave controller
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