82374EB datasheet(162/208 Pages) INTEL

162 / 208 page

82374EB82374SB

In a cascade configuration the slave interrupt outputs are connected to the master interrupt request inputs

When a slave request line is activated and afterwards acknowledged the master will enable the corresponding

slave to release the interrupt vector address during the second INTA

cycle of the interrupt acknowledge

sequence

Each Interrupt Controller in the cascaded system must follow a separate initialization sequence and can be

programmed to work in a different mode An EOI command must be issued twice once for the master and

once for the slave

967 EDGE AND LEVEL TRIGGERED MODES

There are two ELCR registers one for each 82C59 bank They are located at IO ports 04D0h (for the Master

Bank IRQ 0137 ) and 04D1h (for the Slave Bank IRQ 8

15 ) They allow the edge and level sense

selection to be made on an interrupt by interrupt basis instead of on a complete bank Only the interrupts that

connect to the EISA bus may be programmed for level sensitivity That is IRQ (0128

13) must be pro-

grammed for edge sensitive operation The LTIM bit is disabled in the ESC The default programming is

equivalent to programming the LTIM bit (ICW1 bit 3) to a 0

If an ELCR bit is equal to ‘‘0’’ an interrupt request will be recognized by a low to high transition on the

corresponding IRQ input The IRQ input can remain high without generating another interrupt

If an ELCR bit is equal to ‘‘1’’ an interrupt request will be recognized by a ‘‘low’’ level on the corresponding

IRQ input and there is no need for an edge detection For level triggered interrupt mode the interrupt request

signal must be removed before the EOI command is issued or the CPU interrupt must be disabled This is

necessary to prevent a second interrupt from occurring

In both the edge and level triggered modes the IRQ inputs must remain active until after the falling edge of the

first INTA

If the IRQ input goes inactive before this time a DEFAULT IRQ7 will occur when the CPU

acknowledges the interrupt This can be a useful safeguard for detecting interrupts caused by spurious noise

glitches on the IRQ inputs To implement this feature the IRQ7 routine is used for ‘‘clean up’’ simply executing

a return instruction thus ignoring the interrupt If IRQ7 is needed for other purposes a default IRQ7 can still be

detected by reading the ISR A normal IRQ7 interrupt will set the corresponding ISR bit a default IRQ7 won’t

If a default IRQ7 routine occurs during a normal IRQ7 routine however the ISR will remain set In this case it is

necessary to keep track of whether or not the IRQ7 routine was previously entered If another IRQ7 occurs it is

a default

IRQ13 still appears externally to be an edge sensitive interrupt even though it is shared internally with the

Chaining interrupt The Chaining interrupt is ORed after the edge sense logic

97 Register Functionality

For a detailed description of the Interrupt Controller register set please see Section 34 Interrupt Controller

971 INITIALIZATION COMMAND WORDS

Four initialization command words (ICWs) are used to initialize each interrupt controller Each controller is

initialized separately Following this initialization sequence the interrupt controller is ready to accept interrupts

162

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