82374EB datasheet(166/208 Pages) INTEL

166 / 208 page

82374EB82374SB

100 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

In addition to the standard EISA compatible interrupt controller described in the previous section the ESC

incorporates the Advanced Programmable Interrupt Controller (APIC) While the standard interrupt controller is

intended for use in a uni-processor system APIC can be used in either a uni-processor or multi-processor

system APIC provides multi-processor interrupt management and incorporates both static and dynamic sym-

metric interrupt distribution across all processors In systems with multiple IO subsystems each subsystem

can have its own set of interrupts

In a uni-processor system APIC’s dedicated interrupt bus can reduce interrupt latency over the standard

interrupt controller (ie the latency associated with the propagation of the interrupt acknowledge cycle across

multiple busses using the standard interrupt controller approach) Interrupts can be controlled by the standard

EISA compatible interrupt controller unit the IO APIC unit or mixed mode where both the standard and IO

APIC are used The selection of which controller responds to an interrupt is determined by how the interrupt

controllers are programmed Note that it is the programmer’s responsibility to make sure that the same

interrupt input signal is not handled by both interrupt controllers

At the system level APIC consists of two parts (Figure 23)one residing in the IO subsystem (called the IO

APIC) and the other in the CPU (called the Local APIC) The ESC contains an IO APIC unit The local APIC

and the IO APIC communicate over a dedicated APIC bus The ESC’s IO APIC bus interface consists of two

bi-directional data signals (APICD 10 ) and a clock input (APICCLK)

The CPU’s Local APIC Unit contains the necessary intelligence to determine whether or not its processor

should accept interrupts broadcast on the APIC bus The Local Unit also provides local pending of interrupts

nesting and masking of interrupts and handles all interactions with its local processor (eg the INTRINTA

EOI protocol) The Local Unit further provides inter-processor interrupts and a timer to its local processor The

290476 – D6

Figure 23 APIC System Structure

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82374EB Datasheet(PDF) 166 Page - Intel Corporation