82374EB datasheet(167/208 Pages) INTEL

167 / 208 page

82374EB82374SB

The ESC’s IO APIC Unit consists of a set of interrupt input signals a 16-entry Interrupt Redirection Table

programmable registers and a message unit for sending and receiving APIC messages over the APIC bus

(Figure 24) IO devices inject interrupts into the system by asserting one of the interrupt lines to the IO APIC

(Figure 25) The IO APIC selects the corresponding entry in the Redirection Table and uses the information in

that entry to format an interrupt request message Each entry in the Redirection Table can be individually

programmed to indicate edgelevel sensitive interrupt signals the interrupt vector and priority the destination

processor and how the processor is selected (statically or dynamically) The information in the table is used to

transmit a message to other APIC units (via the APIC bus)

The ESC’s IO APIC contains a set of programmable registers Two of the registers (IO Register Select and

IO Window Registers) are located in the CPU’s memory space and are used to indirectly access the other

APIC registers as described in Section 30 Register Description The Version Register provides the implemen-

tation version of the IO APIC The IO APIC ID Register is programmed with an ID value that serves as a

physical name of the IO APIC This ID is loaded into the ARB ID Register when the IO APIC ID Register is

written and is used during bus arbitration

NOTE

1 When the ESC’s IO APIC receives an interrupt request the ESC instructs the PCEB to flush its

buffers and to request all system buffers pointing to PCI to be flushed (via the AFLUSH

signal) The

APIC does not send the interrupt message over the APIC bus until the ESC receives confirmation

from the PCEB (via the AFLUSH

signal) that all buffers have been flushed and temporarily disabled

2 The interrupt number or the vector does not imply a particular priority for being sent The IO APIC

continually polls the 16 interrupts in a rotating fashion one at a time The pending interrupt polled first

is the one sent

290476 – D7

Figure 24 APIC Register Block Diagram

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82374EB Datasheet(PDF) 167 Page - Intel Corporation