82374EB datasheet(169/208 Pages) INTEL

169 / 208 page

82374EB82374SB

A bus arbitration cycle starts by the agent driving a start cycle (bit 1eEOI bit 0e1) on the APIC bus (Table

29) Bit 1e1 indicates ‘‘EOI’’ priority and bit 1e0 indicates normal priority Bit 0 should be 1

In cycles 2 through 5 the agent drives the arbitration ID on bit 1 of the bus High-order ID bits are driven first

with successive cycles proceeding to the low bits of the ID All arbitration losers in a given cycle drop off the

bus using every subsequent cycle as a tie breaker for the previous cycle When all arbitration cycles are

completed there will be only one agent left driving the bus

Table 29 Bus Arbitration Cycles

Cycle

Bit 1

Bit 0

Comments

EOI

0 1 e normal 1 1 e EOI

ArbID3

Arbitration ID bits 3 through 0

ArbID2

ArbID1

ArbID0

103 Bus Message Formats

After bus arbitration the winner is granted exclusive use of the bus and drives its message on the bus APIC

messages come in four formats14 cycle EOI Message 21 cycles Short Message 33 cycles Lowest Priority

Message and 39 cycles Remote Read Message All APICs on the APIC bus know the length of an interrupt

message by checking the appropriate fields in the message

EOI Message For Level Triggered Interrupts

The EOI Message is used to send an EOI cycle occurring for a level triggered interrupt from local APIC to the

IO APIC This cycle contains the priority vector (V 70 ) of the interrupt When this message is received the

IO APIC resets the Remote IRR bit for that interrupt If the interrupt signal is still active after the RIRR bit is

reset the IO APIC will treat it as a new interrupt

Table 30 EOI Message

Cycle

Bit 1

Bit 0

Comments

EOI

0 1 e normal 1 1 e EOI

ArbID3

Arbitration ID bits 3 through 0

ArbID2

ArbID1

ArbID0

Interrupt vector V7 – V0

7V5

8V3

9V1

169

82374EB Datasheet(PDF) 169 Page - Intel Corporation

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