82374EB datasheet(170/208 Pages) INTEL

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82374EB82374SB

Table 30 EOI Message

(Continued)

Cycle

Bit 1

Bit 0

Comments

Check Sum

Postamble

Status Cycle0

Status Cycle1

Idle

Short Message

Short Messages are used for the delivery of Fixed NMI SMI (82374SB only) Reset ExtINT and Lowest

Priority with Focus processor interrupts The delivery mode bits (M 20 ) specify the message All short mes-

sages take 21 cycles including the idle cycle

Cycle 1 is the start cycle (Table 31) Cycles 2 through 5 are for bus arbitration as described earlier APIC ID bits

are sent on the bus one bit at a time (Only one data bus bit is used) The other bit should be zero Cycles 6 and

7 provide destination mode and delivery mode bits Cycle 8 provides level and trigger mode information

Cycles 10 through 13 are the 8-bit interrupt vector The vector is only defined for delivery modes fixed and

lowest-priority For delivery mode of ‘‘Remote Read’’ the vector field contains the address of the register to be

read remotely

If Destination Mode (DM) is 0 (physical mode) then cycles 15 and 16 are the APIC ID and cycles 13 and 14 are

zero If DM is 1 (logical mode) then cycles 13 through 16 are the 8-bit destination field The interpretation of

the logical mode 8-bit destination field is performed by the local units using the Destination Format Register

Shorthands of ‘‘all-incl-self’’ and ‘‘all-excl-self’’ both use physical destination mode and a destination field

containing APIC ID value of all ones The sending APIC knows whether it should (incl) or should not (excl)

respond to its own message

Cycle 17 is a checksum for the data in cycles 6 through 16 The (single) APIC driving the message provides

this checksum in cycle 17

Cycle 18 is a postamble cycle driven as 00 by all APICs to perform various internal computations based on the

information contained in the received message One of the computations takes the computed checksum of the

data received in cycles 6 through 16 and compares it against the value in cycle 17 If any APIC computes a

different checksum than the one passed in cycle 17 then that APIC signals an error on the APIC bus in cycle

19 by driving it as 11 If this happens all APICs assume the message was never sent and the sender must try

sending the message again which includes re-arbitrating for the APIC bus In lowest priority delivery when the

interrupt has a focus processor the focus processor signals this by driving 10 during cycle 19 This tells all the

other APICs that the interrupt has been accepted the LP arbitration is preempted and short message format

is used Cycle 19 and 20 indicates the status of the message (ie accepted check sum error retry or error)

Table 32 shows the status signals combinations and their meanings for all delivery modes

The checksum is calculated iteratively on each cycle by adding the following terms

1 The two least significant bits from the last cycle’s checksum

2 The current two data bits

3 The carry bit from the last cycle’s checksum shifted to the least significant bit

Note that at the beginning of the calculation the three bits composing the previous cycle’s checksum (two

lower bits and carry) are zero

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