82374EB datasheet(173/208 Pages) INTEL

173 / 208 page

82374EB82374SB

Lowest Priority (LP) without Focus Processor (FP) Message

This message format is used to deliver an interrupt in the lowest priority mode in which it does not have a

Focus Processor Cycles 1 through 20 for this message are the same as for the Short Message discussed

above Status cycle 19 identifies if there is not a Focus processor (00) and a status value of 11 in cycle 20

indicates the need for lowest priority arbitration

Cycle 21 through 28 are used to arbitrate for the lowest priority processor The processors that take part in the

arbitration drive their processor priority on the bus Only the local APICs that have ‘‘free interrupt slots’’

participate in the lowest priority arbitration

Cycle 29 through 32 are used to break a tie in case two or more processors have lowest priority The bus

arbitration IDs are used to break the tie

Cycle 33 is an additional status cycle driven by the accepting local APIC By receiving 10 during this cycle the

sending IO APIC knows that there was a local APIC left after LP arbitration Otherwise the message is

retried Cycle 34 is an idle cycle

Table 33 Lowest Priority without Focus Processor Message

Cycle

Bit 1

Bit 0

0 1 e normal 1 1 e EOI

ArbID3

Arbitration ID bits 3 through 0

ArbID2

ArbID1

ArbID0

6DM

DM e Destination mode

M2–M0 e Delivery mode

L e Level TM e Trigger Mode

V7–V0 e Interrupt Vector

Destination

Checksum for cycles 6-16

Postamble

Status cycle 0

Status cycle 1

173

82374EB Datasheet(PDF) 173 Page - Intel Corporation