82374EB datasheet(165/208 Pages) INTEL

165 / 208 page

82374EB82374SB

Software Events

1 Software Generated NMI If an IO Write access to Port 0462h occurs The data value for this write is

a don’t care

The NMI logic incorporates four different 8-bit registers These registers are used by the CPU to determine the

source of the interrupt and to enable or disableclear the interrupts See Section 34 Interrupt Controller

Registers for the register details

Table 27 NMI Register IO Address Map

IO Port Address

0061h

NMI Status Register

0070h

NMI Enable Register

0461h

Extended NMI Register

0462h

Software NMI Register

Table 28 NMI Source EnableDisable And Status Port Bits

NMI Source

IO Port Bit for Status Reads

IO Port Bit for EnableDisable

PERR

Port 0061h Bit 7

Port 0061h Bit 2

IOCHK

Port 0061h Bit 6

Port 0061h Bit 3

Fail-Safe

Port 0461h Bit 7

Port 0461h Bit 2

Bus Timeout

Port 0461h Bit 6

Port 0461h Bit 3

Write to Port 0462h

Port 0461h Bit 5

Port 0461h Bit 1

The individual enabledisable bits clear the NMI detect flip-flops when disabled

All NMI sources can be enabled or disabled by setting Port 070h bit 7

This disable function does not clear

the NMI detect Flip-Flops This means if NMI is disabled then enabled via Port 070h then an NMI will occur

when Port 070h is re-enabled if one of the NMI detect Flip-Flops had been previously set

To ensure that all NMI requests are serviced the NMI service routine software needs to incorporate a few very

specific requirements These requirements are due to the edge detect circuitry of the host microprocessor

80386 or 80486 The software flow would need to be the following

1 NMI is detected by the processor on the rising edge of the NMI input

2 The processor will read the status stored in port 061h and 0461h to determine what sources caused the

NMI The processor may then reset the register bits controlling the sources that it has determined to be

active Between the time the processor reads the NMI sources and resets them an NMI may have been

generated by another source The level of NMI will then remain active This new NMI source will not be

recognized by the processor because there was no edge on NMI

3 The processor must then disable all NMI’s by writing bit 7 of port 070H high and then enable all NMI’s by

writing bit 7 of port 070H low This will cause the NMI output to transition low then high if there are any

pending NMI sources The CPU’s NMI input logic will then register a new NMI

165

82374EB Datasheet(PDF) 165 Page - Intel Corporation

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