AD7147 datasheet(38/73 Pages) AD

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Data Sheet

AD7147

Rev. D | Page 37 of 72

SDA

DEV

R/W

SCLK

DEV

ACK

A15

A14

678

910

START

AD7147-1 DEVICE ADDRESS

ACK

D15

D14

ACK

STOP

DEV

START

AD7147-1 DEVICE ADDRESS

NOTES

1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.

2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.

3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X IS A DON’T CARE BIT.

4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X IS A DON’T CARE BIT.

5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.

6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.

Figure 53. Example of I2C Timing for Single Register Write Operation

Writing Data over the I2C Bus

The process for writing to the AD7147-1 over the I2C bus is

shown in Figure 53 and Figure 55. The device address is sent

over the bus, followed by the R/W bit being set to 0 and then

two bytes of data that contain the 10-bit address of the internal

data register to be written. The following bit map shows the

upper register address bytes. Note that Bit 7 to Bit 2 in the upper

address byte are don’t care bits. The address is contained in the

10 LSBs of the register address bytes.

MSB

LSB

Address

Bit 9

Address

Bit 8

The following bit map shows the lower register address bytes.

MSB

LSB

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

The third data byte contains the eight MSBs of the data to be

written to the internal register. The fourth data byte contains

the eight LSBs of data to be written to the internal register.

The AD7147-1 address pointer register automatically increments

after each write. This allows the master to sequentially write to all

registers on the AD7147-1 in the same write transaction. However,

the address pointer register does not wrap around after the last

address. Therefore, any data written to the AD7147-1 after the

address pointer has reached its maximum value is discarded.

All registers on the AD7147-1 are 16 bits. Two consecutive 8-bit

data bytes are combined and written to the 16-bit registers. To

avoid errors, all writes to the device must contain an even

number of data bytes.

To finish the transaction, the master generates a stop condition

on SDO, or generates a repeat start condition if the master is to

maintain control of the bus.

Reading Data over the I2C Bus

To read from the AD7147-1, the address pointer register must

first be set to the address of the required internal register. The

master performs a write transaction, and then writes to the

AD7147-1 to set the address pointer. Next, the master outputs a

repeat start condition to keep control of the bus, or if this is not

possible, ends the write transaction with a stop condition. A read

transaction is initiated, with the R/W bit set to 1.

The AD7147-1 supplies the upper eight bits of data from the

addressed register in the first readback byte, followed by the

lower eight bits in the next byte. This is shown in Figure 54 and

Figure 55.

Because the address pointer automatically increments after each

read, the AD7147-1 continues to output readback data until the

master sends a no acknowledge and stop condition to the bus. If

the address pointer reaches its maximum value and the master

continues to read from the part, the AD7147-1 repeatedly sends

data from the last register that was addressed.

AD7147 Datasheet(PDF) 38 Page - Analog Devices

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