ISL6142CB datasheet(5/23 Pages) INTERSIL

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VEE Pin 7 - This is the most Negative Supply Voltage, such

as in a -48V system. Most of the other signals are referenced

relative to this pin, even though it may be far away from what

is considered a GND reference.

SENSE Pin 8 - This analog input monitors the voltage drop

across the external sense resistor to determine if the current

flowing through it exceeds the programmed Over-Current trip

point (50mV / Rsense). If the Over-Current threshold is

exceeded, the circuit will regulate the current to maintain a

nominal voltage drop of 50mV across the R1 sense resistor,

also referred to as Rsense. If current is limited for more than

the programmed time-out period the

IntelliTripTM electronic

circuit breaker will trip and turn off the FET.

A second comparator is employed to detect and respond

quickly to hard faults. The threshold of this comparator is set

approximately four times higher (210mV) than the Over-

Current trip point. When the hard fault comparator threshold

is exceeded the GATE is immediately (10

µs typical) shut off

(VGATE = VEE), the timer is reset, and a single retry (soft

start) is initiated.

IS+ Pin 9 - This analog pin is the positive input of the current

sense circuit. A sensing resistor (R8) is connected between

this pin and the output side of R1, which is also connected to

the SENSE pin. It should match the IS- resistor (R7) as

closely as possible (1%) to minimize output current error

(ISOUT). If current sensing is not used in the application, the

IS+ pin should be tied directly to the IS- pin and the node

should be left floating.

GATE Pin 10 -

This analog output drives the gate of the

external FET used as a pass transistor. The GATE pin is high

(FET is on) when the following conditions are met:

•VDD UVLO is above its trip point (~16.5V)

• Voltage on the UV pin is above its trip point (1.255V)

• Voltage on the OV pin is below its trip point (1.255V)

• No Over-Current conditions are present.

• The Disable pin is low.

If any of the 5 conditions are violated, the GATE pin will be

pulled low to shut off or regulate current through the FET.

The GATE is latched off only when an Over-Current event

exceeds the programmed time-out period.

The GATE is driven high by a weak (-50

µA nominal) pull-up

current source, in order to slowly turn on the FET. It is driven

low by a 70mA (nominal) pull-down device for three of the

above shut-off conditions. A larger (350mA nominal) pull-

down current shuts off the FET very quickly in the event of a

hard fault where the sense pin voltage exceeds

approximately 210mV.

DRAIN Pin 11 - This analog input monitors the voltage of

the FET drain for the Power Good function. The DRAIN input

is tied to two comparators with internal reference voltages of

1.3v and 8.0V. At initial start-up the DRAIN to VEE voltage

differential must be less than 1.3V, and the GATE voltage

must be within 2.5V of its normal operating voltage (13.6V)

for power to be considered good. When both conditions are

met, the PWRGD/PWRGD output is latched into the active

state. At this point only the 8V DRAIN comparator can

control the PWRGD/PWRGD output, and will drive it inactive

if the DRAIN voltage exceeds VEE by more than 8.0V.

ISOUT Pin 12 - This analog pin is the output of the current

sense circuit. The current flowing out of this pin (ISOUT) is

proportional to the current flowing through the R1 sense

resistor (ISENSE). The scaling factor, ISOUT/ISENSE is

defined by the resistor ratio of R1/R7. Current to voltage

conversion is accomplished by placing a resistor from this

pin to -VIN. The current flowing out of the pin is supplied by

the internal 13V regulator and should not exceed 600

µA.

The output voltage will clamp at approximately 8V. If current

sensing is not used in the application the pin should be left

open.

CT Pin 13 - This analog I/O pin is used to program the Over-

Current Time-Out period with a capacitor connected to the

negative supply rail (-VIN which is equal to VEE). During

normal operation, the pin is pulled down to VEE. During

current limiting, the capacitor is charged with a 20

µA

(nominal) current source. When the CT pin charges to 8.5V,

it times out and the GATE is latched off. If the short circuit

goes away prior to the time-out, the GATE will remain on. If

no capacitor is connected, the time-out will be much quicker,

with only the package pin capacitance (~ 5 to 10 pF) to

charge. If no external capacitor is connected to the CT pin

the time-out will occur in a few

µsec. To set the desired time-

out period use:

dt = (C * dV) / I = (C * 8.5) / 20

µA = 0.425*106 * C

NOTE: The printed circuit board’s parasitic capacitance (CT pin to

the negative input, -VIN) should be taken into consideration when

calculating the value of C3 needed for the desired time-out.

VDD Pin 14 - This is the most positive Power Supply pin. It

can range from the Under-Voltage lockout threshold (16.5V)

to +80V (Relative to VEE). The pin can tolerate up to 100V

without damage to the IC.

ISL6142, ISL6152

ISL6142CB Datasheet(PDF) 5 Page - Intersil Corporation

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