ISL6142CB datasheet(19/23 Pages) INTERSIL

19 / 23 page

be found, then consider 2 separate resistor dividers (one for

each pin, both from VDD to -VIN). This also allows the user to

adjust or trim either trip point independently. Some

applications employ a short pin ground on the connector tied

to R4 to ensure the hot plug device is fully powered up

before the UV and OV pins (tied to the short pin ground) are

biased. This ensures proper control of the GATE is

maintained during power up. This is not a requirement for the

ISL6142/52 however the circuit will perform properly if a

short pin scheme is implemented (reference Figure 38).

Applications: PWRGD/PWRGD

The PWRGD/PWRGD outputs are typically used to directly

enable a power module, such as a DC/DC converter. The

PWRGD (ISL6142) is used for modules with active low

enable (L version), and PWRGD (ISL6152) for those with an

active high enable (H version). The modules usually have a

pull-up device built-in, as well as an internal clamp. If not, an

external pull-up resistor may be needed. If the pin is not

used, it can be left open.

For both versions at initial start-up, when the DRAIN to VEE

voltage differential is less than 1.3V and the GATE voltage is

within 2.5V (VGH) of its normal operating voltage (13.6V),

power is considered good and the PWRGD/PWRGD pins

will go active. At this point the output is latched and the

comparators above no longer control the output. However a

second DRAIN comparator remains active and will drive the

PWRGD/PWRGD output inactive if the DRAIN voltage

exceeds VEE by more than 8V. The latch is reset by any of

the signals that shut off the GATE (Over-Voltage, Under-

Voltage; Under-Voltage-Lock-Out; Over-Current Time-Out,

disable pin high, or powering down). In this case the

PWRGD/PWRGD output will go inactive, indicating power is

no longer good.

ISL6142 (L version; Figure 34): Under normal conditions

(DRAIN voltage - VEE < VPG, and ∆VGATE - VGATE < VGH)

the Q2 DMOS will turn on, pulling PWRGD low, enabling the

module.

When any of the 5 conditions occur that turn off the GATE

(OV, UV, UVLO, Over-Current Time-Out, disable pin high)

the PWRGD latch is reset and the Q2 DMOS device will shut

off (high impedance). The pin will quickly be pulled high by

the external module (or an optional pull-up resistor or

equivalent) which in turn will disable it. If a pull-up resistor is

used, it can be connected to any supply voltage that doesn’t

exceed the IC pin maximum ratings on the high end, but is

high enough to give acceptable logic levels to whatever

signal it is driving. An external clamp may be used to limit the

voltage range.

The PWRGD can also drive an opto-coupler (such as a

4N25), as shown in Figure 35 or LED (Figure 36). In both

cases, they are on (active) when power is good. Resistors

R13 or R14 are chosen based on the supply voltage, and the

amount of current needed by the loads.

ISL6152 (H version; Figure 37): Under normal conditions

(DRAIN voltage - VEE < VPG, and ∆VGATE - VGATE < VGH),

the Q3 DMOS will be on, shorting the bottom of the internal

resistor to VEE, turning Q2 off. If the pull-up current from the

external module is high enough, the voltage drop across the

6.2k

Ω resistor will look like a logic high (relative to DRAIN).

Note that the module is only referenced to DRAIN, not VEE

FIGURE 34. ACTIVE LOW ENABLE MODULE

VEE

PWRGD

DRAIN

VDD

VIN+

VIN-

ON/OFF

VOUT+

VOUT-

ACTIVE LOW

ENABLE

MODULE

(SECTION OF) ISL6142

(L VERSION)

VPG

VEE

GATE

∆ V

GATE

LOGIC

LATCH

VGH

VDH

VEE

OPTO

PWRGD

FIGURE 35. ACTIVE LOW ENABLE OPTO-ISOLATOR

R13

VEE

VDD

(SECTION OF) ISL6142

(L VERSION)

PWRGD

DRAIN

LOGIC

LATCH

COMPARATORS

FIGURE 36. ACTIVE LOW ENABLE LED

R14

VEE

VDD

(SECTION OF) ISL6142

(L VERSION)

PWRGD

DRAIN

LOGIC

LATCH

COMPARATORS

LED (GREEN)

ISL6142, ISL6152

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