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AN2823 Datasheet(PDF) 9 Page - STMicroelectronics |
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AN2823 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 33 page ![]() AN2823 The L5973AD in LED driving applications Doc ID 15015 Rev 1 9/33 The current source schematic in Figure 7 shows a negligible value for the output capacitor to achieve better performance in the dimming operation. The high switching frequency of the L5973AD helps to keep the unfiltered current ripple in the LED negligible compared to the DC current, so the color shift of the emitted light in all operating conditions can be considered negligible. The L5973AD is based on a voltage mode control loop. Therefore, the duty ratio of the internal switch is obtained through a comparison between a sawtooth waveform (generated by an oscillator) and the output voltage of the error amplifier (see Figure 6). The embedded error amplifier is a transconductance type so its output stage delivers current to the compensation network. Figure 6. Block diagram of L5973AD In Figure 7, the output of the embedded transconductance error amplifier is clamped by switch Q1, in accordance with the PWM signal. When switch Q1 is ON, the COMP pin is low (see Figure 9). Regardless of the FB input there is no intersection between the internal sawtooth waveform and the output of the error amplifier. The internal switch is thus disabled and the inductor current starts decreasing down to zero. When the PWM signal disables the Q1 switch (see Figure 10), no current flows in the sense resistor RS, so the error amplifier is highly unbalanced and free to charge the compensation network composed of C4, C5 and R5. When the voltage of the COMP pin crosses the internal sawtooth ramp, the embedded switch is enabled: the current source starts charging the inductor and the rising edge phase of the LED begins. The minimum voltage of the internal sawtooth waveform is about 1 V (see the voltage mode architecture in Figure 8) so there is a time delay between the disabling of the Q1 switch and the first pulse of the internal MOSFET. The delay is due to the time necessary to charge the compensation network to the minimum voltage to cross the internal ramp. This provides a shift between the duty cycle of the input PWM signal and the real PWM dimming performed on the load current. Figure 9 and Figure 10 show the dimming operation monitoring the input dimming signal and the LED current. AM01357v1 |
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