AN4382 datasheet(13/70 Pages) STMICROELECTRONICS

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AN4382

PFC stage

3.3

Implementation on STLUX385A

The PFC stage is implemented exploiting the SMED technology used in the STLUX385A. In

particular, two SMEDs, used in a coupled mode, are used to drive a single PWM output

connected to the PFC MOSFET.

In Table 1 is the list of the STLUX385A inputs and outputs used for the PFC stage:

Figure 6 offers a system view on STLUX385A PFC implementation:

Figure 6. PFC logical implementation

The STLUX385A embeds the algorithms used to control the PFC behavior by regulating the

PWM switching frequency. The correct switching parameters (Ton, Toff) are calculated

starting from the PFC output voltage.

The system calculates the difference between the actual (ADC0) and the target (Vref) PFC

output voltage. The error is firstly filtered by a 5 Hz low-pass filter obtaining a dynamic gain

factor ranging from 1 x to 6 x. Every 100

μs, the new working parameters (Ton or Toff,

depending on the load condition) are calculated by adding the error, amplified by the gain, to

the current parameters. The output voltage is filtered by a 200 ms moving average window

Table 1. List of STLUX385A pins used by the PFC stage

Description

PWM5

Used as a PWM for the PFC MOSFET. It is internally driven by the SMED4 and SMED5

CPP0

Input for OVP protection

CPP2

Senses the current during Ton time

ADC0

PFC output voltage measurement

ADC3

Input voltage, phase and frequency measurement

DGIN3

“Zero Current Detection” input

DGIN2

Input THD optimizer

AN4382 Datasheet(PDF) 13 Page - STMicroelectronics