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AN4382 Datasheet(PDF) 23 Page - STMicroelectronics |
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AN4382 Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 70 page  DocID025437 Rev 1 23/70 AN4382 ZVS LC resonant stage description 70 Figure 11. Half bridge logical implementation The control stage algorithm of the half bridge resonator makes sure that the half bridge is always driven at the correct frequency so that the amount of current sensed (CPP3) matches the target current (Iref) as selected by the user via the DALI, UART or the 0/10 interface. The high precision signal generated by the PWM2 is used as a comparison with the actual current. The control loop bandwidth is 10 KHz. The minimum allowed frequency is 70 KHz and maximum frequency is 400 KHz. The STLUX385A limits the resonant output current increases or decreases rate to a maximum of 300 mA /second, in order to preserve both the output capacitors and the LED string. |
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